From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Lara Lazier <laramglazier@gmail.com>
Subject: [PULL 02/36] target/i386: Added VGIF feature
Date: Mon, 6 Sep 2021 15:10:25 +0200 [thread overview]
Message-ID: <20210906131059.55234-3-pbonzini@redhat.com> (raw)
In-Reply-To: <20210906131059.55234-1-pbonzini@redhat.com>
From: Lara Lazier <laramglazier@gmail.com>
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210730070742.9674-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 3 ++-
target/i386/svm.h | 6 ++++++
target/i386/tcg/sysemu/svm_helper.c | 31 +++++++++++++++++++++++++++--
3 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fbca4e5860..86064ea1f9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -631,7 +631,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_EXT4_FEATURES 0
-#define TCG_SVM_FEATURES CPUID_SVM_NPT
+#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
+ CPUID_SVM_SVME_ADDR_CHK)
#define TCG_KVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
diff --git a/target/i386/svm.h b/target/i386/svm.h
index adc058dc76..036597a2ff 100644
--- a/target/i386/svm.h
+++ b/target/i386/svm.h
@@ -9,6 +9,12 @@
#define V_IRQ_SHIFT 8
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
+#define V_GIF_ENABLED_SHIFT 25
+#define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT)
+
+#define V_GIF_SHIFT 9
+#define V_GIF_MASK (1 << V_GIF_SHIFT)
+
#define V_INTR_PRIO_SHIFT 16
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index 0e7de4e054..66c2c1e61f 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -121,6 +121,17 @@ static inline bool is_efer_invalid_state (CPUX86State *env)
return false;
}
+static inline bool virtual_gif_enabled(CPUX86State *env, uint32_t *int_ctl)
+{
+ if (likely(env->hflags & HF_GUEST_MASK)) {
+ *int_ctl = x86_ldl_phys(env_cpu(env),
+ env->vm_vmcb + offsetof(struct vmcb, control.int_ctl));
+ return (env->features[FEAT_SVM] & CPUID_SVM_VGIF)
+ && (*int_ctl & V_GIF_ENABLED_MASK);
+ }
+ return false;
+}
+
void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
{
CPUState *cs = env_cpu(env);
@@ -510,13 +521,29 @@ void helper_vmsave(CPUX86State *env, int aflag)
void helper_stgi(CPUX86State *env)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0, GETPC());
- env->hflags2 |= HF2_GIF_MASK;
+
+ CPUState *cs = env_cpu(env);
+ uint32_t int_ctl;
+ if (virtual_gif_enabled(env, &int_ctl)) {
+ x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
+ int_ctl | V_GIF_MASK);
+ } else {
+ env->hflags2 |= HF2_GIF_MASK;
+ }
}
void helper_clgi(CPUX86State *env)
{
cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0, GETPC());
- env->hflags2 &= ~HF2_GIF_MASK;
+
+ CPUState *cs = env_cpu(env);
+ uint32_t int_ctl;
+ if (virtual_gif_enabled(env, &int_ctl)) {
+ x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
+ int_ctl & ~V_GIF_MASK);
+ } else {
+ env->hflags2 &= ~HF2_GIF_MASK;
+ }
}
bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
--
2.31.1
next prev parent reply other threads:[~2021-09-06 13:15 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-06 13:10 [PULL 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-06 13:10 ` [PULL 01/36] target/i386: VMRUN and VMLOAD canonicalizations Paolo Bonzini
2021-09-06 13:10 ` Paolo Bonzini [this message]
2021-09-06 13:10 ` [PULL 03/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini
2021-09-06 13:10 ` [PULL 04/36] target/i386: Added VGIF V_IRQ masking capability Paolo Bonzini
2021-09-06 13:10 ` [PULL 05/36] target/i386: Added ignore TPR check in ctl_has_irq Paolo Bonzini
2021-09-06 13:10 ` [PULL 06/36] target/i386: Added changed priority check for VIRQ Paolo Bonzini
2021-09-06 13:10 ` [PULL 07/36] target/i386: Added vVMLOAD and vVMSAVE feature Paolo Bonzini
2021-09-06 13:10 ` [PULL 08/36] configure / meson: Move the GBM handling to meson.build Paolo Bonzini
2021-09-06 13:26 ` Thomas Huth
2021-09-06 13:10 ` [PULL 09/36] memory: Add RAM_PROTECTED flag to skip IOMMU mappings Paolo Bonzini
2021-09-06 13:10 ` [PULL 10/36] hostmem: Add hostmem-epc as a backend for SGX EPC Paolo Bonzini
2021-09-07 6:23 ` Yang Zhong
2021-09-06 13:10 ` [PULL 11/36] qom: Add memory-backend-epc ObjectOptions support Paolo Bonzini
2021-09-06 13:10 ` [PULL 12/36] i386: Add 'sgx-epc' device to expose EPC sections to guest Paolo Bonzini
2021-09-06 13:10 ` [PULL 13/36] vl: Add sgx compound properties to expose SGX " Paolo Bonzini
2021-09-06 13:10 ` [PULL 14/36] i386: Add primary SGX CPUID and MSR defines Paolo Bonzini
2021-09-06 13:10 ` [PULL 15/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX Paolo Bonzini
2021-09-06 13:10 ` [PULL 16/36] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX Paolo Bonzini
2021-09-06 13:10 ` [PULL 17/36] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX Paolo Bonzini
2021-09-06 13:10 ` [PULL 18/36] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs Paolo Bonzini
2021-09-06 13:10 ` [PULL 19/36] i386: Add feature control MSR dependency when SGX is enabled Paolo Bonzini
2021-09-06 13:10 ` [PULL 20/36] i386: Update SGX CPUID info according to hardware/KVM/user input Paolo Bonzini
2021-09-06 13:10 ` [PULL 21/36] i386: kvm: Add support for exposing PROVISIONKEY to guest Paolo Bonzini
2021-09-06 13:10 ` [PULL 22/36] i386: Propagate SGX CPUID sub-leafs to KVM Paolo Bonzini
2021-09-06 13:10 ` [PULL 23/36] Adjust min CPUID level to 0x12 when SGX is enabled Paolo Bonzini
2021-09-06 13:10 ` [PULL 24/36] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Paolo Bonzini
2021-09-06 13:10 ` [PULL 25/36] hw/i386/pc: Account for SGX EPC sections when calculating device memory Paolo Bonzini
2021-09-06 13:10 ` [PULL 26/36] i386/pc: Add e820 entry for SGX EPC section(s) Paolo Bonzini
2021-09-06 13:10 ` [PULL 27/36] i386: acpi: Add SGX EPC entry to ACPI tables Paolo Bonzini
2021-09-06 13:10 ` [PULL 28/36] q35: Add support for SGX EPC Paolo Bonzini
2021-09-06 13:10 ` [PULL 29/36] i440fx: " Paolo Bonzini
2021-09-06 13:10 ` [PULL 30/36] hostmem-epc: Add the reset interface for EPC backend reset Paolo Bonzini
2021-09-06 13:10 ` [PULL 31/36] sgx-epc: Add the reset interface for sgx-epc virt device Paolo Bonzini
2021-09-06 13:10 ` [PULL 32/36] sgx-epc: Avoid bios reset during sgx epc initialization Paolo Bonzini
2021-09-06 13:10 ` [PULL 33/36] hostmem-epc: Make prealloc consistent with qemu cmdline during reset Paolo Bonzini
2021-09-06 13:10 ` [PULL 34/36] Kconfig: Add CONFIG_SGX support Paolo Bonzini
2021-09-06 13:10 ` [PULL 35/36] sgx-epc: Add the fill_device_info() callback support Paolo Bonzini
2021-09-06 13:10 ` [PULL 36/36] doc: Add the SGX doc Paolo Bonzini
2021-09-06 14:03 ` [PULL 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210906131059.55234-3-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=laramglazier@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).