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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Lara Lazier <laramglazier@gmail.com>
Subject: [PULL v4 07/43] target/i386: Added changed priority check for VIRQ
Date: Wed,  8 Sep 2021 12:03:50 +0200	[thread overview]
Message-ID: <20210908100426.264356-8-pbonzini@redhat.com> (raw)
In-Reply-To: <20210908100426.264356-1-pbonzini@redhat.com>

From: Lara Lazier <laramglazier@gmail.com>

Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.h                    | 15 +++++++++++++++
 target/i386/tcg/sysemu/misc_helper.c |  7 +++++++
 target/i386/tcg/sysemu/svm_helper.c  | 15 ---------------
 3 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 24e8ec5273..6b09b8b62f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2246,6 +2246,21 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env)
     return reserved_bits;
 }
 
+static inline bool ctl_has_irq(CPUX86State *env)
+{
+    uint32_t int_prio;
+    uint32_t tpr;
+
+    int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
+    tpr = env->int_ctl & V_TPR_MASK;
+
+    if (env->int_ctl & V_IGN_TPR_MASK) {
+        return (env->int_ctl & V_IRQ_MASK);
+    }
+
+    return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
+}
+
 #if defined(TARGET_X86_64) && \
     defined(CONFIG_USER_ONLY) && \
     defined(CONFIG_LINUX)
diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c
index 91b0fc916b..9ccaa054c4 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -122,6 +122,13 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
             qemu_mutex_unlock_iothread();
         }
         env->int_ctl = (env->int_ctl & ~V_TPR_MASK) | (t0 & V_TPR_MASK);
+
+        CPUState *cs = env_cpu(env);
+        if (ctl_has_irq(env)) {
+            cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
+        } else {
+            cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
+        }
         break;
     default:
         env->cr[reg] = t0;
diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c
index a35b79548a..7bbd3a18c9 100644
--- a/target/i386/tcg/sysemu/svm_helper.c
+++ b/target/i386/tcg/sysemu/svm_helper.c
@@ -76,21 +76,6 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
                            sc->base, sc->limit, sc->flags);
 }
 
-static inline bool ctl_has_irq(CPUX86State *env)
-{
-    uint32_t int_prio;
-    uint32_t tpr;
-
-    int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
-    tpr = env->int_ctl & V_TPR_MASK;
-
-    if (env->int_ctl & V_IGN_TPR_MASK) {
-        return env->int_ctl & V_IRQ_MASK;
-    }
-
-    return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
-}
-
 static inline bool is_efer_invalid_state (CPUX86State *env)
 {
     if (!(env->efer & MSR_EFER_SVME)) {
-- 
2.31.1




  parent reply	other threads:[~2021-09-08 10:06 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 10:03 [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 01/43] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 02/43] target/i386: VMRUN and VMLOAD canonicalizations Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 03/43] target/i386: Added VGIF feature Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 04/43] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 05/43] target/i386: Added VGIF V_IRQ masking capability Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 06/43] target/i386: Added ignore TPR check in ctl_has_irq Paolo Bonzini
2021-09-08 10:03 ` Paolo Bonzini [this message]
2021-09-08 10:03 ` [PULL v4 08/43] target/i386: Added vVMLOAD and vVMSAVE feature Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 09/43] memory: Add RAM_PROTECTED flag to skip IOMMU mappings Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 10/43] hostmem: Add hostmem-epc as a backend for SGX EPC Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 11/43] qom: Add memory-backend-epc ObjectOptions support Paolo Bonzini
2021-09-08 14:51   ` Eric Blake
2021-09-08 10:03 ` [PULL v4 12/43] i386: Add 'sgx-epc' device to expose EPC sections to guest Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 13/43] vl: Add sgx compound properties to expose SGX " Paolo Bonzini
2021-09-08 14:52   ` Eric Blake
2021-09-09  3:01     ` Yang Zhong
2021-09-08 10:03 ` [PULL v4 14/43] i386: Add primary SGX CPUID and MSR defines Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 15/43] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX Paolo Bonzini
2021-09-08 10:03 ` [PULL v4 16/43] i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 17/43] i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 18/43] i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 19/43] fw_cfg: add etc/msr_feature_control Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 20/43] i386: Add feature control MSR dependency when SGX is enabled Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 21/43] i386: Update SGX CPUID info according to hardware/KVM/user input Paolo Bonzini
2021-09-09 13:09   ` Philippe Mathieu-Daudé
2021-09-08 10:04 ` [PULL v4 22/43] i386: kvm: Add support for exposing PROVISIONKEY to guest Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 23/43] i386: Propagate SGX CPUID sub-leafs to KVM Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 24/43] Adjust min CPUID level to 0x12 when SGX is enabled Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 25/43] hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 26/43] hw/i386/pc: Account for SGX EPC sections when calculating device memory Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 27/43] i386/pc: Add e820 entry for SGX EPC section(s) Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 28/43] i386: acpi: Add SGX EPC entry to ACPI tables Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 29/43] q35: Add support for SGX EPC Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 30/43] i440fx: " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 31/43] hostmem-epc: Add the reset interface for EPC backend reset Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 32/43] sgx-epc: Add the reset interface for sgx-epc virt device Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 33/43] sgx-epc: Avoid bios reset during sgx epc initialization Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 34/43] hostmem-epc: Make prealloc consistent with qemu cmdline during reset Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 35/43] Kconfig: Add CONFIG_SGX support Paolo Bonzini
2021-09-09 13:16   ` Philippe Mathieu-Daudé
2021-09-09 13:33     ` Philippe Mathieu-Daudé
2021-09-08 10:04 ` [PULL v4 36/43] sgx-epc: Add the fill_device_info() callback support Paolo Bonzini
2021-09-08 14:54   ` Eric Blake
2021-09-08 10:04 ` [PULL v4 37/43] docs: standardize book titles to === with overline Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 38/43] docs: standardize directory index to --- " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 39/43] docs/system: standardize man page sections " Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 40/43] docs/system: move x86 CPU configuration to a separate document Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 41/43] docs/system: Add SGX documentation to the system manual Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 42/43] meson.build: Do not look for VNC-related libraries if have_system is not set Paolo Bonzini
2021-09-08 10:04 ` [PULL v4 43/43] ebpf: only include in system emulators Paolo Bonzini
2021-09-09 13:25 ` [PULL v4 00/43] (Mostly) x86 changes for 2021-09-06 Peter Maydell
2021-09-09 13:32   ` Philippe Mathieu-Daudé
2021-09-11 12:59 ` Peter Maydell
2021-09-11 13:05   ` Paolo Bonzini

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