From: Atish Patra <atish.patra@wdc.com>
To: qemu-devel@nongnu.org
Cc: Atish Patra <atish.patra@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function
Date: Thu, 9 Sep 2021 13:26:31 -0700 [thread overview]
Message-ID: <20210909202639.1230170-2-atish.patra@wdc.com> (raw)
In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. Ideally, they should check the mcountern
bits before cycle/minstret/hpmcounterx access. The predicate function
also calculates the counter index incorrectly for hpmcounterx.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/csr.c | 62 +++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 58 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac597..0515d851b948 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -62,12 +62,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_is_32bit(env)) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
@@ -89,8 +141,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -116,8 +169,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.31.1
next prev parent reply other threads:[~2021-09-09 20:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 20:26 [ RFC v2 0/9] Improve PMU support Atish Patra
2021-09-09 20:26 ` Atish Patra [this message]
2021-09-15 14:49 ` [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function Bin Meng
2021-09-16 18:39 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 4:49 ` Alistair Francis
2021-09-09 20:26 ` [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 18:52 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 18:47 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 5/9] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2021-09-09 20:26 ` [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation Atish Patra
2021-09-09 20:26 ` [ RFC v2 7/9] target/riscv: Add sscofpmf extension support Atish Patra
2021-09-09 20:26 ` [ RFC v2 8/9] target/riscv: Add few cache related PMU events Atish Patra
2021-09-09 20:26 ` [ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
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