From: Atish Patra <atish.patra@wdc.com>
To: qemu-devel@nongnu.org
Cc: Atish Patra <atish.patra@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [ RFC v2 8/9] target/riscv: Add few cache related PMU events
Date: Thu, 9 Sep 2021 13:26:38 -0700 [thread overview]
Message-ID: <20210909202639.1230170-9-atish.patra@wdc.com> (raw)
In-Reply-To: <20210909202639.1230170-1-atish.patra@wdc.com>
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f49..c86250e1aada 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,10 +21,13 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "pmu.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
+#include "cpu.h"
+#include "cpu_bits.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -754,6 +757,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
}
#endif /* !CONFIG_USER_ONLY */
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+ enum riscv_pmu_event_idx pmu_event_type;
+
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+ break;
+ case MMU_DATA_LOAD:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+ break;
+ case MMU_DATA_STORE:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+ break;
+ default:
+ return;
+ }
+
+ riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -851,6 +876,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
}
} else {
+ pmu_tlb_fill_incr_ctr(cpu, access_type);
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
access_type, mmu_idx, true, false, false);
--
2.31.1
next prev parent reply other threads:[~2021-09-09 20:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 20:26 [ RFC v2 0/9] Improve PMU support Atish Patra
2021-09-09 20:26 ` [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 18:39 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 4:49 ` Alistair Francis
2021-09-09 20:26 ` [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 18:52 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-09-15 14:49 ` Bin Meng
2021-09-16 18:47 ` Atish Patra
2021-09-09 20:26 ` [ RFC v2 5/9] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2021-09-09 20:26 ` [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation Atish Patra
2021-09-09 20:26 ` [ RFC v2 7/9] target/riscv: Add sscofpmf extension support Atish Patra
2021-09-09 20:26 ` Atish Patra [this message]
2021-09-09 20:26 ` [ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
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