From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/23] hw/char: cadence_uart: Disable transmit when input clock is disabled
Date: Mon, 13 Sep 2021 17:11:23 +0100 [thread overview]
Message-ID: <20210913161144.12347-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210913161144.12347-1-peter.maydell@linaro.org>
From: Bin Meng <bmeng.cn@gmail.com>
At present when input clock is disabled, any character transmitted
to tx fifo can still show on the serial line, which is wrong.
Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210901124521.30599-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/cadence_uart.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index b4b5e8a3ee0..154be34992b 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -327,6 +327,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond,
static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
int size)
{
+ /* ignore characters when unclocked or in reset */
+ if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) {
+ return;
+ }
+
if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
return;
}
--
2.20.1
next prev parent reply other threads:[~2021-09-13 16:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 16:11 [PULL 00/23] target-arm queue Peter Maydell
2021-09-13 16:11 ` [PULL 01/23] hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase Peter Maydell
2021-09-13 16:11 ` Peter Maydell [this message]
2021-09-13 16:11 ` [PULL 03/23] hw/char: cadence_uart: Move clock/reset check to uart_can_receive() Peter Maydell
2021-09-13 16:11 ` [PULL 04/23] hw/char: cadence_uart: Convert to memop_with_attrs() ops Peter Maydell
2021-09-13 16:11 ` [PULL 05/23] hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() Peter Maydell
2021-09-13 16:11 ` [PULL 06/23] hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Peter Maydell
2021-09-13 16:11 ` [PULL 07/23] hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell
2021-09-13 16:11 ` [PULL 08/23] hw/arm: Add support for kudo-bmc board Peter Maydell
2021-09-13 16:11 ` [PULL 09/23] hw/intc: GICv3 ITS initial framework Peter Maydell
2021-09-13 16:11 ` [PULL 10/23] hw/intc: GICv3 ITS register definitions added Peter Maydell
2021-09-13 16:11 ` [PULL 11/23] hw/intc: GICv3 ITS command queue framework Peter Maydell
2021-09-13 16:11 ` [PULL 12/23] hw/intc: GICv3 ITS Command processing Peter Maydell
2021-09-13 16:11 ` [PULL 13/23] hw/intc: GICv3 ITS Feature enablement Peter Maydell
2021-09-13 16:11 ` [PULL 14/23] hw/intc: GICv3 redistributor ITS processing Peter Maydell
2021-09-13 16:11 ` [PULL 15/23] tests/data/acpi/virt: Add IORT files for ITS Peter Maydell
2021-09-13 16:11 ` [PULL 16/23] hw/arm/virt: add ITS support in virt GIC Peter Maydell
2021-09-13 16:11 ` [PULL 17/23] tests/data/acpi/virt: Update IORT files for ITS Peter Maydell
2021-09-13 16:11 ` [PULL 18/23] target/arm: Take an exception if PSTATE.IL is set Peter Maydell
2021-09-13 16:11 ` [PULL 19/23] target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Peter Maydell
2021-09-13 16:11 ` [PULL 20/23] qdev: Support marking individual buses as 'full' Peter Maydell
2021-09-13 16:11 ` [PULL 21/23] hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn Peter Maydell
2021-09-13 16:11 ` [PULL 22/23] hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' Peter Maydell
2021-09-13 16:11 ` [PULL 23/23] hw/arm/mps2.c: " Peter Maydell
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