From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Warner Losh" <imp@bsdimp.com>
Subject: [PULL 19/44] target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
Date: Mon, 13 Sep 2021 17:14:31 -0700 [thread overview]
Message-ID: <20210914001456.793490-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210914001456.793490-1-richard.henderson@linaro.org>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Following the logic of commit 30493a030ff ("i386: split seg_helper
into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
under sysemu/seg_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Message-Id: <20210911165434.531552-12-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/seg_helper.c | 64 -----------------------------
target/i386/tcg/sysemu/seg_helper.c | 62 ++++++++++++++++++++++++++++
2 files changed, 62 insertions(+), 64 deletions(-)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 4e6f26a7b7..baa905a0cd 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -1110,70 +1110,6 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw);
}
-#ifndef CONFIG_USER_ONLY
-bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
- int intno;
-
- interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
- if (!interrupt_request) {
- return false;
- }
-
- /* Don't process multiple interrupt requests in a single call.
- * This is required to make icount-driven execution deterministic.
- */
- switch (interrupt_request) {
- case CPU_INTERRUPT_POLL:
- cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
- apic_poll_irq(cpu->apic_state);
- break;
- case CPU_INTERRUPT_SIPI:
- do_cpu_sipi(cpu);
- break;
- case CPU_INTERRUPT_SMI:
- cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
- cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
- do_smm_enter(cpu);
- break;
- case CPU_INTERRUPT_NMI:
- cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
- cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
- env->hflags2 |= HF2_NMI_MASK;
- do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
- break;
- case CPU_INTERRUPT_MCE:
- cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
- do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
- break;
- case CPU_INTERRUPT_HARD:
- cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
- cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_VIRQ);
- intno = cpu_get_pic_interrupt(env);
- qemu_log_mask(CPU_LOG_TB_IN_ASM,
- "Servicing hardware INT=0x%02x\n", intno);
- do_interrupt_x86_hardirq(env, intno, 1);
- break;
- case CPU_INTERRUPT_VIRQ:
- cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
- intno = x86_ldl_phys(cs, env->vm_vmcb
- + offsetof(struct vmcb, control.int_vector));
- qemu_log_mask(CPU_LOG_TB_IN_ASM,
- "Servicing virtual hardware INT=0x%02x\n", intno);
- do_interrupt_x86_hardirq(env, intno, 1);
- cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
- env->int_ctl &= ~V_IRQ_MASK;
- break;
- }
-
- /* Ensure that no TB jump will be modified as the program flow was changed. */
- return true;
-}
-#endif /* CONFIG_USER_ONLY */
-
void helper_lldt(CPUX86State *env, int selector)
{
SegmentCache *dt;
diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c
index 82c0856c41..bf3444c26b 100644
--- a/target/i386/tcg/sysemu/seg_helper.c
+++ b/target/i386/tcg/sysemu/seg_helper.c
@@ -125,6 +125,68 @@ void x86_cpu_do_interrupt(CPUState *cs)
}
}
+bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ int intno;
+
+ interrupt_request = x86_cpu_pending_interrupt(cs, interrupt_request);
+ if (!interrupt_request) {
+ return false;
+ }
+
+ /* Don't process multiple interrupt requests in a single call.
+ * This is required to make icount-driven execution deterministic.
+ */
+ switch (interrupt_request) {
+ case CPU_INTERRUPT_POLL:
+ cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ apic_poll_irq(cpu->apic_state);
+ break;
+ case CPU_INTERRUPT_SIPI:
+ do_cpu_sipi(cpu);
+ break;
+ case CPU_INTERRUPT_SMI:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0);
+ cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
+ do_smm_enter(cpu);
+ break;
+ case CPU_INTERRUPT_NMI:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0);
+ cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ env->hflags2 |= HF2_NMI_MASK;
+ do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
+ break;
+ case CPU_INTERRUPT_MCE:
+ cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
+ do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
+ break;
+ case CPU_INTERRUPT_HARD:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0);
+ cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_VIRQ);
+ intno = cpu_get_pic_interrupt(env);
+ qemu_log_mask(CPU_LOG_TB_IN_ASM,
+ "Servicing hardware INT=0x%02x\n", intno);
+ do_interrupt_x86_hardirq(env, intno, 1);
+ break;
+ case CPU_INTERRUPT_VIRQ:
+ cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0);
+ intno = x86_ldl_phys(cs, env->vm_vmcb
+ + offsetof(struct vmcb, control.int_vector));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM,
+ "Servicing virtual hardware INT=0x%02x\n", intno);
+ do_interrupt_x86_hardirq(env, intno, 1);
+ cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ env->int_ctl &= ~V_IRQ_MASK;
+ break;
+ }
+
+ /* Ensure that no TB jump will be modified as the program flow was changed. */
+ return true;
+}
+
/* check if Port I/O is allowed in TSS */
void helper_check_io(CPUX86State *env, uint32_t addr, uint32_t size)
{
--
2.25.1
next prev parent reply other threads:[~2021-09-14 0:21 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-14 0:14 [PULL 00/44] tcg patch queue, v2 Richard Henderson
2021-09-14 0:14 ` [PULL 01/44] accel/tcg: Add DisasContextBase argument to translator_ld* Richard Henderson
2021-09-14 0:14 ` [PULL 02/44] accel/tcg: Clear PAGE_WRITE before translation Richard Henderson
2021-09-14 0:14 ` [PULL 03/44] tcg/i386: Split P_VEXW from P_REXW Richard Henderson
2021-09-14 0:14 ` [PULL 04/44] accel/tcg: remove redundant TCG_KICK_PERIOD define Richard Henderson
2021-09-14 0:14 ` [PULL 05/44] tcg: Remove tcg_global_reg_new defines Richard Henderson
2021-09-14 0:14 ` [PULL 06/44] tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN Richard Henderson
2021-09-14 0:14 ` [PULL 07/44] tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF Richard Henderson
2021-09-14 0:14 ` [PULL 08/44] tcg/arm: Fix tcg_out_vec_op function signature Richard Henderson
2021-09-14 0:14 ` [PULL 09/44] target/avr: Remove pointless use of CONFIG_USER_ONLY definition Richard Henderson
2021-09-14 0:14 ` [PULL 10/44] target/i386: Restrict sysemu-only fpu_helper helpers Richard Henderson
2021-09-14 0:14 ` [PULL 11/44] target/i386: Simplify TARGET_X86_64 #ifdef'ry Richard Henderson
2021-09-14 0:14 ` [PULL 12/44] target/xtensa: Restrict do_transaction_failed() to sysemu Richard Henderson
2021-09-14 0:14 ` [PULL 13/44] accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt Richard Henderson
2021-09-14 0:14 ` [PULL 14/44] target/alpha: Restrict cpu_exec_interrupt() handler to sysemu Richard Henderson
2021-09-14 0:14 ` [PULL 15/44] target/arm: " Richard Henderson
2021-09-14 0:14 ` [PULL 16/44] target/cris: " Richard Henderson
2021-09-14 0:14 ` [PULL 17/44] target/hppa: " Richard Henderson
2021-09-14 0:14 ` [PULL 18/44] target/i386: " Richard Henderson
2021-09-14 0:14 ` Richard Henderson [this message]
2021-09-14 0:14 ` [PULL 20/44] target/m68k: " Richard Henderson
2021-09-14 0:14 ` [PULL 21/44] target/microblaze: " Richard Henderson
2021-09-14 0:14 ` [PULL 22/44] target/mips: " Richard Henderson
2021-09-14 0:14 ` [PULL 23/44] target/nios2: " Richard Henderson
2021-09-14 0:14 ` [PULL 24/44] target/openrisc: " Richard Henderson
2021-09-14 0:14 ` [PULL 25/44] target/ppc: " Richard Henderson
2021-09-14 0:14 ` [PULL 26/44] target/riscv: " Richard Henderson
2021-09-14 0:14 ` [PULL 27/44] target/sh4: " Richard Henderson
2021-09-14 0:14 ` [PULL 28/44] target/sparc: " Richard Henderson
2021-09-14 0:14 ` [PULL 29/44] target/rx: " Richard Henderson
2021-09-14 0:14 ` [PULL 30/44] target/xtensa: " Richard Henderson
2021-09-14 0:14 ` [PULL 31/44] accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() " Richard Henderson
2021-09-14 0:14 ` [PULL 32/44] user: Remove cpu_get_pic_interrupt() stubs Richard Henderson
2021-09-14 0:14 ` [PULL 33/44] user: Mark cpu_loop() with noreturn attribute Richard Henderson
2021-09-14 0:14 ` [PULL 34/44] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts Richard Henderson
2021-09-14 0:14 ` [PULL 35/44] tcg/arm: Remove fallback definition of __ARM_ARCH Richard Henderson
2021-09-14 5:58 ` Philippe Mathieu-Daudé
2021-09-14 0:14 ` [PULL 36/44] tcg/arm: Standardize on tcg_out_<branch>_{reg,imm} Richard Henderson
2021-09-14 0:14 ` [PULL 37/44] tcg/arm: Simplify use_armv5t_instructions Richard Henderson
2021-09-14 0:14 ` [PULL 38/44] tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call Richard Henderson
2021-09-14 0:14 ` [PULL 39/44] tcg/arm: Split out tcg_out_ldstm Richard Henderson
2021-09-14 0:14 ` [PULL 40/44] tcg/arm: Simplify usage of encode_imm Richard Henderson
2021-09-14 0:14 ` [PULL 41/44] tcg/arm: Drop inline markers Richard Henderson
2021-09-14 0:14 ` [PULL 42/44] tcg/arm: Give enum arm_cond_code_e a typedef and use it Richard Henderson
2021-09-14 0:14 ` [PULL 43/44] tcg/arm: More use of the ARMInsn enum Richard Henderson
2021-09-14 0:14 ` [PULL 44/44] tcg/arm: More use of the TCGReg enum Richard Henderson
2021-09-14 12:39 ` [PULL 00/44] tcg patch queue, v2 Peter Maydell
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