* [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends
@ 2021-09-15 8:46 Bin Meng
2021-09-16 4:42 ` Alistair Francis
2021-09-16 21:41 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Bin Meng @ 2021-09-15 8:46 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 8 ++++----
target/riscv/csr.c | 24 ++++++++++++------------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7330ff5a19..34564d367c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -397,10 +397,10 @@
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
-#define HCOUNTEREN_CY (1 << 0)
-#define HCOUNTEREN_TM (1 << 1)
-#define HCOUNTEREN_IR (1 << 2)
-#define HCOUNTEREN_HPM3 (1 << 3)
+#define COUNTEREN_CY (1 << 0)
+#define COUNTEREN_TM (1 << 1)
+#define COUNTEREN_IR (1 << 2)
+#define COUNTEREN_HPM3 (1 << 3)
/* Privilege modes */
#define PRV_U 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 50a2c3a3b4..1cd34a6453 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
- if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
- get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ if (!get_field(env->hcounteren, COUNTEREN_CY) &&
+ get_field(env->mcounteren, COUNTEREN_CY)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
case CSR_TIME:
- if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
- get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ if (!get_field(env->hcounteren, COUNTEREN_TM) &&
+ get_field(env->mcounteren, COUNTEREN_TM)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
case CSR_INSTRET:
- if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
- get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ if (!get_field(env->hcounteren, COUNTEREN_IR) &&
+ get_field(env->mcounteren, COUNTEREN_IR)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
if (riscv_cpu_is_32bit(env)) {
switch (csrno) {
case CSR_CYCLEH:
- if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
- get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ if (!get_field(env->hcounteren, COUNTEREN_CY) &&
+ get_field(env->mcounteren, COUNTEREN_CY)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
case CSR_TIMEH:
- if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
- get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ if (!get_field(env->hcounteren, COUNTEREN_TM) &&
+ get_field(env->mcounteren, COUNTEREN_TM)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
case CSR_INSTRETH:
- if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
- get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ if (!get_field(env->hcounteren, COUNTEREN_IR) &&
+ get_field(env->mcounteren, COUNTEREN_IR)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-15 8:46 [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends Bin Meng
@ 2021-09-16 4:42 ` Alistair Francis
2021-09-16 21:41 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-09-16 4:42 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Sep 15, 2021 at 6:47 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
> in fact it applies to M-mode and S-mode CSR too. Rename these macros
> to have the COUNTEREN_ prefix.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu_bits.h | 8 ++++----
> target/riscv/csr.c | 24 ++++++++++++------------
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7330ff5a19..34564d367c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -397,10 +397,10 @@
> #define HSTATUS32_WPRI 0xFF8FF87E
> #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
>
> -#define HCOUNTEREN_CY (1 << 0)
> -#define HCOUNTEREN_TM (1 << 1)
> -#define HCOUNTEREN_IR (1 << 2)
> -#define HCOUNTEREN_HPM3 (1 << 3)
> +#define COUNTEREN_CY (1 << 0)
> +#define COUNTEREN_TM (1 << 1)
> +#define COUNTEREN_IR (1 << 2)
> +#define COUNTEREN_HPM3 (1 << 3)
>
> /* Privilege modes */
> #define PRV_U 0
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 50a2c3a3b4..1cd34a6453 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_virt_enabled(env)) {
> switch (csrno) {
> case CSR_CYCLE:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIME:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRET:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> @@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_is_32bit(env)) {
> switch (csrno) {
> case CSR_CYCLEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIMEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRETH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-15 8:46 [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends Bin Meng
2021-09-16 4:42 ` Alistair Francis
@ 2021-09-16 21:41 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-09-16 21:41 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Sep 15, 2021 at 6:47 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
> in fact it applies to M-mode and S-mode CSR too. Rename these macros
> to have the COUNTEREN_ prefix.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> target/riscv/cpu_bits.h | 8 ++++----
> target/riscv/csr.c | 24 ++++++++++++------------
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7330ff5a19..34564d367c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -397,10 +397,10 @@
> #define HSTATUS32_WPRI 0xFF8FF87E
> #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
>
> -#define HCOUNTEREN_CY (1 << 0)
> -#define HCOUNTEREN_TM (1 << 1)
> -#define HCOUNTEREN_IR (1 << 2)
> -#define HCOUNTEREN_HPM3 (1 << 3)
> +#define COUNTEREN_CY (1 << 0)
> +#define COUNTEREN_TM (1 << 1)
> +#define COUNTEREN_IR (1 << 2)
> +#define COUNTEREN_HPM3 (1 << 3)
>
> /* Privilege modes */
> #define PRV_U 0
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 50a2c3a3b4..1cd34a6453 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_virt_enabled(env)) {
> switch (csrno) {
> case CSR_CYCLE:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIME:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRET:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> @@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_is_32bit(env)) {
> switch (csrno) {
> case CSR_CYCLEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIMEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRETH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-09-15 8:46 [PATCH] target/riscv: csr: Rename HCOUNTEREN_CY and friends Bin Meng
2021-09-16 4:42 ` Alistair Francis
2021-09-16 21:41 ` Alistair Francis
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