From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: david@redhat.com
Subject: [PATCH v5 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec
Date: Wed, 15 Sep 2021 14:31:13 -0700 [thread overview]
Message-ID: <20210915213114.1923776-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210915213114.1923776-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.h | 2 +-
tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 49b98f33b9..426dd92e51 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -26,6 +26,7 @@ C_O1_I2(r, r, ri)
C_O1_I2(r, rZ, r)
C_O1_I2(v, v, r)
C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
C_O1_I4(r, r, ri, r, 0)
C_O1_I4(r, r, ri, rI, 0)
C_O2_I2(b, a, 0, r)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index a79f4f187a..527ada0f63 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -157,7 +157,7 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
/* used for function call generation */
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 4a56532011..5530c974a6 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -296,6 +296,7 @@ typedef enum S390Opcode {
VRRa_VUPH = 0xe7d7,
VRRa_VUPL = 0xe7d6,
VRRc_VX = 0xe76d,
+ VRRe_VSEL = 0xe78d,
VRRf_VLVGP = 0xe762,
VRSa_VERLL = 0xe733,
@@ -647,6 +648,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
}
+static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op,
+ TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
+{
+ tcg_debug_assert(is_vector_reg(v1));
+ tcg_debug_assert(is_vector_reg(v2));
+ tcg_debug_assert(is_vector_reg(v3));
+ tcg_debug_assert(is_vector_reg(v4));
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
+ tcg_out16(s, v3 << 12);
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12));
+}
+
static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
TCGReg v1, TCGReg r2, TCGReg r3)
{
@@ -2787,6 +2800,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
break;
+ case INDEX_op_bitsel_vec:
+ tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+ break;
+
case INDEX_op_cmp_vec:
switch ((TCGCond)args[3]) {
case TCG_COND_EQ:
@@ -2827,6 +2844,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_add_vec:
case INDEX_op_and_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_bitsel_vec:
case INDEX_op_neg_vec:
case INDEX_op_not_vec:
case INDEX_op_or_vec:
@@ -3168,6 +3186,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
return C_O1_I2(v, v, r);
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(v, v, v, v);
default:
g_assert_not_reached();
--
2.25.1
next prev parent reply other threads:[~2021-09-15 21:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 21:30 [PATCH v5 00/16] tcg/s390x: host vector support Richard Henderson
2021-09-15 21:30 ` [PATCH v5 01/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2021-09-17 11:24 ` Matheus K. Ferst
2021-09-17 13:46 ` Richard Henderson
2021-09-15 21:31 ` [PATCH v5 02/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2021-09-16 5:19 ` Thomas Huth
2021-09-16 5:27 ` Philippe Mathieu-Daudé
2021-09-15 21:31 ` [PATCH v5 03/16] tcg/s390x: Change FACILITY representation Richard Henderson
2021-09-15 21:31 ` [PATCH v5 04/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2021-09-15 21:31 ` [PATCH v5 05/16] tcg/s390x: Add host vector framework Richard Henderson
2021-09-15 21:31 ` [PATCH v5 06/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2021-09-16 8:09 ` David Hildenbrand
2021-09-15 21:31 ` [PATCH v5 07/16] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2021-09-15 21:31 ` [PATCH v5 08/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2021-09-15 21:31 ` [PATCH v5 09/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2021-09-15 21:31 ` [PATCH v5 10/16] tcg/s390x: Implement andc, orc, abs, neg, not " Richard Henderson
2021-09-16 8:12 ` David Hildenbrand
2021-09-15 21:31 ` [PATCH v5 11/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-09-15 21:31 ` [PATCH v5 12/16] tcg/s390x: Implement vector shift operations Richard Henderson
2021-09-15 21:31 ` [PATCH v5 13/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-09-15 21:31 ` [PATCH v5 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-09-15 21:31 ` Richard Henderson [this message]
2021-09-15 21:31 ` [PATCH v5 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
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