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Thu, 16 Sep 2021 08:30:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id b7sm3779447pgs.64.2021.09.16.08.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Sep 2021 08:30:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 00/35] tcg patch queue Date: Thu, 16 Sep 2021 08:29:50 -0700 Message-Id: <20210916153025.1944763-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 57b6f58c1d0df757c9311496c32d502925056894: Merge remote-tracking branch 'remotes/hreitz/tags/pull-block-2021-09-15' into staging (2021-09-15 18:55:59 +0100) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210916 for you to fetch changes up to 50febfe212f24a9b91b4224d03f653415fddf8e1: tcg/mips: Drop special alignment for code_gen_buffer (2021-09-16 09:37:39 -0400) ---------------------------------------------------------------- Restrict cpu_has_work to sysemu, and move to AccelOpsClass. Move cpu_signal_handler declaration out of target/. Misc tcg/mips/ cleanups. ---------------------------------------------------------------- Philippe Mathieu-Daudé (30): accel/tcg: Restrict cpu_handle_halt() to sysemu hw/core: Restrict cpu_has_work() to sysemu hw/core: Un-inline cpu_has_work() sysemu: Introduce AccelOpsClass::has_work() accel/kvm: Implement AccelOpsClass::has_work() accel/whpx: Implement AccelOpsClass::has_work() accel/tcg: Implement AccelOpsClass::has_work() as stub target/alpha: Restrict has_work() handler to sysemu target/arm: Restrict has_work() handler to sysemu and TCG target/avr: Restrict has_work() handler to sysemu target/cris: Restrict has_work() handler to sysemu target/hexagon: Remove unused has_work() handler target/hppa: Restrict has_work() handler to sysemu target/i386: Restrict has_work() handler to sysemu and TCG target/m68k: Restrict has_work() handler to sysemu target/microblaze: Restrict has_work() handler to sysemu target/mips: Restrict has_work() handler to sysemu and TCG target/nios2: Restrict has_work() handler to sysemu target/openrisc: Restrict has_work() handler to sysemu target/ppc: Introduce PowerPCCPUClass::has_work() target/ppc: Restrict has_work() handlers to sysemu and TCG target/riscv: Restrict has_work() handler to sysemu and TCG target/rx: Restrict has_work() handler to sysemu target/s390x: Restrict has_work() handler to sysemu and TCG target/sh4: Restrict has_work() handler to sysemu target/sparc: Remove pointless use of CONFIG_TCG definition target/sparc: Restrict has_work() handler to sysemu target/tricore: Restrict has_work() handler to sysemu target/xtensa: Restrict has_work() handler to sysemu accel: Add missing AccelOpsClass::has_work() and drop SysemuCPUOps one Richard Henderson (5): include/exec: Move cpu_signal_handler declaration tcg/mips: Drop inline markers tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr tcg/mips: Unset TCG_TARGET_HAS_direct_jump tcg/mips: Drop special alignment for code_gen_buffer include/exec/exec-all.h | 13 +++++ include/hw/core/cpu.h | 28 ++++------ include/hw/core/tcg-cpu-ops.h | 4 ++ include/sysemu/accel-ops.h | 5 ++ target/alpha/cpu.h | 6 --- target/arm/cpu.h | 7 --- target/avr/cpu.h | 2 - target/cris/cpu.h | 8 --- target/hexagon/cpu.h | 3 -- target/hppa/cpu.h | 3 -- target/i386/cpu.h | 7 --- target/m68k/cpu.h | 8 --- target/microblaze/cpu.h | 7 --- target/mips/cpu.h | 3 -- target/mips/internal.h | 2 - target/nios2/cpu.h | 2 - target/openrisc/cpu.h | 2 - target/ppc/cpu-qom.h | 3 ++ target/ppc/cpu.h | 7 --- target/riscv/cpu.h | 2 - target/rx/cpu.h | 4 -- target/s390x/cpu.h | 7 --- target/sh4/cpu.h | 3 -- target/sparc/cpu.h | 2 - target/tricore/cpu.h | 2 - target/xtensa/cpu.h | 2 - tcg/mips/tcg-target.h | 12 ++--- accel/hvf/hvf-accel-ops.c | 6 +++ accel/kvm/kvm-accel-ops.c | 6 +++ accel/qtest/qtest.c | 6 +++ accel/tcg/cpu-exec.c | 6 ++- accel/tcg/tcg-accel-ops.c | 12 +++++ accel/xen/xen-all.c | 6 +++ hw/core/cpu-common.c | 6 --- softmmu/cpus.c | 10 ++-- target/alpha/cpu.c | 4 +- target/arm/cpu.c | 7 ++- target/avr/cpu.c | 2 +- target/cris/cpu.c | 4 +- target/hexagon/cpu.c | 6 --- target/hppa/cpu.c | 4 +- target/i386/cpu.c | 6 --- target/i386/hax/hax-accel-ops.c | 6 +++ target/i386/nvmm/nvmm-accel-ops.c | 6 +++ target/i386/tcg/tcg-cpu.c | 8 ++- target/i386/whpx/whpx-accel-ops.c | 6 +++ target/m68k/cpu.c | 4 +- target/microblaze/cpu.c | 8 +-- target/mips/cpu.c | 4 +- target/nios2/cpu.c | 4 +- target/openrisc/cpu.c | 4 +- target/ppc/cpu_init.c | 37 ++++++++++---- target/riscv/cpu.c | 8 ++- target/rx/cpu.c | 4 +- target/s390x/cpu.c | 4 +- target/sh4/cpu.c | 5 +- target/sparc/cpu.c | 6 +-- target/tricore/cpu.c | 6 ++- target/xtensa/cpu.c | 14 ++--- tcg/region.c | 91 --------------------------------- tcg/mips/tcg-target.c.inc | 105 +++++++++++++------------------------- 61 files changed, 233 insertions(+), 342 deletions(-)