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charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=886e160e1=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The following changes since commit d1fe59377bbbf91dfded1f08ffe3c636e9db8d= c0: Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6= .2-pull-request' into staging (2021-09-16 16:02:31 +0100) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210917 for you to fetch changes up to c14620db9b66de88bb4fef1d0cfc283bb3d53f85: hw/riscv: opentitan: Correct the USB Dev address (2021-09-17 07:43:55 += 1000) ---------------------------------------------------------------- Second RISC-V PR for QEMU 6.2 - ePMP CSR address updates - Convert internal interrupts to use QEMU GPIO lines - SiFive PWM support - Support for RISC-V ACLINT - SiFive PDMA fixes - Update to u-boot instructions for sifive_u - mstatus.SD bug fix for hypervisor extensions - OpenTitan fix for USB dev address ---------------------------------------------------------------- Alistair Francis (9): target/riscv: Update the ePMP CSR address target/riscv: Expose interrupt pending bits as GPIO lines hw/intc: sifive_clint: Use RISC-V CPU GPIO lines hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines hw/timer: Add SiFive PWM support sifive_u: Connect the SiFive PWM device hw/riscv: opentitan: Correct the USB Dev address Anup Patel (4): hw/intc: Rename sifive_clint sources to riscv_aclint sources hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT hw/riscv: virt: Re-factor FDT generation hw/riscv: virt: Add optional ACLINT support to virt machine Bin Meng (2): docs/system/riscv: sifive_u: Update U-Boot instructions target/riscv: csr: Rename HCOUNTEREN_CY and friends Frank Chang (4): hw/dma: sifive_pdma: reset Next* registers when Control.claim is se= t hw/dma: sifive_pdma: claim bit must be set before DMA transactions hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer target/riscv: Backup/restore mstatus.SD bit when virtual register s= wapped Green Wan (1): hw/dma: sifive_pdma: allow non-multiple transaction size transactio= ns LIU Zhiwei (1): target/riscv: Fix satp write docs/system/riscv/sifive_u.rst | 50 ++-- docs/system/riscv/virt.rst | 10 + include/hw/intc/ibex_plic.h | 2 + include/hw/intc/riscv_aclint.h | 80 +++++ include/hw/intc/sifive_clint.h | 60 ---- include/hw/intc/sifive_plic.h | 4 + include/hw/riscv/sifive_u.h | 14 +- include/hw/riscv/virt.h | 2 + include/hw/timer/ibex_timer.h | 2 + include/hw/timer/sifive_pwm.h | 62 ++++ target/riscv/cpu_bits.h | 12 +- hw/dma/sifive_pdma.c | 54 +++- hw/intc/ibex_plic.c | 17 +- hw/intc/riscv_aclint.c | 460 +++++++++++++++++++++++++++++ hw/intc/sifive_clint.c | 287 ------------------ hw/intc/sifive_plic.c | 30 +- hw/riscv/microchip_pfsoc.c | 13 +- hw/riscv/opentitan.c | 13 +- hw/riscv/shakti_c.c | 16 +- hw/riscv/sifive_e.c | 15 +- hw/riscv/sifive_u.c | 68 ++++- hw/riscv/spike.c | 16 +- hw/riscv/virt.c | 654 ++++++++++++++++++++++++++++-------= ------ hw/timer/ibex_timer.c | 17 +- hw/timer/sifive_pwm.c | 468 +++++++++++++++++++++++++++++ target/riscv/cpu.c | 31 ++ target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 26 +- hw/intc/Kconfig | 2 +- hw/intc/meson.build | 2 +- hw/riscv/Kconfig | 13 +- hw/timer/Kconfig | 3 + hw/timer/meson.build | 1 + hw/timer/trace-events | 6 + 34 files changed, 1844 insertions(+), 669 deletions(-) create mode 100644 include/hw/intc/riscv_aclint.h delete mode 100644 include/hw/intc/sifive_clint.h create mode 100644 include/hw/timer/sifive_pwm.h create mode 100644 hw/intc/riscv_aclint.c delete mode 100644 hw/intc/sifive_clint.c create mode 100644 hw/timer/sifive_pwm.c