From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 09/21] sifive_u: Connect the SiFive PWM device
Date: Fri, 17 Sep 2021 07:48:52 +1000 [thread overview]
Message-ID: <20210916214904.734206-10-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210916214904.734206-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Connect the SiFive PWM device and expose it via the device tree.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
---
docs/system/riscv/sifive_u.rst | 1 +
include/hw/riscv/sifive_u.h | 14 ++++++++-
hw/riscv/sifive_u.c | 55 +++++++++++++++++++++++++++++++++-
hw/riscv/Kconfig | 1 +
4 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 01108b5ecc..7c65e9c440 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices:
* 2 QSPI controllers
* 1 ISSI 25WP256 flash
* 1 SD card in SPI mode
+* PWM0 and PWM1
Please note the real world HiFive Unleashed board has a fixed configuration of
1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 2656b39808..f71c90c94c 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -27,6 +27,7 @@
#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
#include "hw/ssi/sifive_spi.h"
+#include "hw/timer/sifive_pwm.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState {
SiFiveSPIState spi0;
SiFiveSPIState spi2;
CadenceGEMState gem;
+ SiFivePwmState pwm[2];
uint32_t serial;
char *cpu_type;
@@ -92,7 +94,9 @@ enum {
SIFIVE_U_DEV_FLASH0,
SIFIVE_U_DEV_DRAM,
SIFIVE_U_DEV_GEM,
- SIFIVE_U_DEV_GEM_MGMT
+ SIFIVE_U_DEV_GEM_MGMT,
+ SIFIVE_U_DEV_PWM0,
+ SIFIVE_U_DEV_PWM1
};
enum {
@@ -126,6 +130,14 @@ enum {
SIFIVE_U_PDMA_IRQ5 = 28,
SIFIVE_U_PDMA_IRQ6 = 29,
SIFIVE_U_PDMA_IRQ7 = 30,
+ SIFIVE_U_PWM0_IRQ0 = 42,
+ SIFIVE_U_PWM0_IRQ1 = 43,
+ SIFIVE_U_PWM0_IRQ2 = 44,
+ SIFIVE_U_PWM0_IRQ3 = 45,
+ SIFIVE_U_PWM1_IRQ0 = 46,
+ SIFIVE_U_PWM1_IRQ1 = 47,
+ SIFIVE_U_PWM1_IRQ2 = 48,
+ SIFIVE_U_PWM1_IRQ3 = 49,
SIFIVE_U_QSPI0_IRQ = 51,
SIFIVE_U_GEM_IRQ = 53
};
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6766edc1d0..f4cde10667 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -17,6 +17,7 @@
* 7) DMA (Direct Memory Access Controller)
* 8) SPI0 connected to an SPI flash
* 9) SPI2 connected to an SD card
+ * 10) PWM0 and PWM1
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -75,6 +76,8 @@ static const MemMapEntry sifive_u_memmap[] = {
[SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 },
+ [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 },
[SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
[SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
[SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
@@ -441,6 +444,38 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/pwm@%lx",
+ (long)memmap[SIFIVE_U_DEV_PWM0].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_DEV_PWM0].base,
+ 0x0, memmap[SIFIVE_U_DEV_PWM0].size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
+ SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/pwm@%lx",
+ (long)memmap[SIFIVE_U_DEV_PWM1].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_DEV_PWM1].base,
+ 0x0, memmap[SIFIVE_U_DEV_PWM1].size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
+ SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_DEV_UART1].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -765,6 +800,8 @@ static void sifive_u_soc_instance_init(Object *obj)
object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
+ object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
+ object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -777,7 +814,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
size_t plic_hart_config_len;
- int i;
+ int i, j;
NICInfo *nd = &nd_table[0];
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
@@ -904,6 +941,22 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
+ /* PWM */
+ for (i = 0; i < 2; i++) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
+ memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
+
+ /* Connect PWM interrupts to the PLIC */
+ for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
+ }
+ }
+
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index ff75add6f3..d56c339ef6 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -69,6 +69,7 @@ config SIFIVE_U
select SIFIVE_UART
select SIFIVE_U_OTP
select SIFIVE_U_PRCI
+ select SIFIVE_PWM
select SSI_M25P80
select SSI_SD
select UNIMP
--
2.31.1
next prev parent reply other threads:[~2021-09-16 21:57 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-16 21:48 [PULL 00/21] riscv-to-apply queue Alistair Francis
2021-09-16 21:48 ` [PULL 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-16 21:48 ` [PULL 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-16 21:48 ` [PULL 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-16 21:48 ` [PULL 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-16 21:48 ` [PULL 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-16 21:48 ` [PULL 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-16 21:48 ` [PULL 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-16 21:48 ` [PULL 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-16 21:48 ` Alistair Francis [this message]
2021-09-16 21:48 ` [PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-16 21:48 ` [PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-16 21:48 ` [PULL 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-16 21:48 ` [PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-16 21:48 ` [PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Alistair Francis
2021-09-16 21:48 ` [PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Alistair Francis
2021-09-16 21:48 ` [PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-16 21:49 ` [PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-16 21:49 ` [PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions Alistair Francis
2021-09-16 21:49 ` [PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-16 21:49 ` [PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends Alistair Francis
2021-09-16 21:49 ` [PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-20 13:19 ` [PULL 00/21] riscv-to-apply queue Peter Maydell
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