From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EE2DC433EF for ; Thu, 16 Sep 2021 21:57:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B9A4760F25 for ; Thu, 16 Sep 2021 21:57:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B9A4760F25 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=opensource.wdc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:42800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mQzNL-0003PJ-UN for qemu-devel@archiver.kernel.org; Thu, 16 Sep 2021 17:56:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQzGi-0005qi-2d for qemu-devel@nongnu.org; Thu, 16 Sep 2021 17:50:09 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:20965) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mQzGe-0002Ow-Ls for qemu-devel@nongnu.org; Thu, 16 Sep 2021 17:50:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1631829004; x=1663365004; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bEGVNCgosMHtUlxH9kOtaXa5oZpBJ9IYzT/i1SohdGA=; b=YW2+hv6pnvwKFBwB36/A93uapQRteM4TW5V+Wjq28wV+B2UvJbhlhYg1 cGN/DxdMYE70CzSlL4CGW055JjAatNxtuQc4z0W/WUC+f9z2NIl6xfeuy /fOGhDwqhaSgeKhLvbjckSLsOL/86Fy3jmpyjS0himeqVgndVMt2vkOCK 2EJz0dr9inJjZ4on4YE9BiaQfS4vkThe8YfAPDNRE5L2D86hPrQ7VemrV nNMj3/uZcd5R+OaaJJWsutTrKP4FQhmuQA7MW0DJSA8vy+u1f2k+yTeB0 kB86Z+1fWZKxPMt0HlVUh7MPs5VLiab/1rEgL3DrURUIrI6GOGwlrMMFd w==; X-IronPort-AV: E=Sophos;i="5.85,299,1624291200"; d="scan'208";a="184998236" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 17 Sep 2021 05:49:58 +0800 IronPort-SDR: ZJFo4xMb9v7HlifIMsGiEGdKO+5fjsLQsxf+bEVTyJ2/QIdNbEasIgy9pTXIYpqJTUIcpZTYAb 7eEIuHO1UL1+NC6nLQbuxhtYQHZMWbZZn5ZLiu9yrT4dV/0cLNJrY4EuernLw3Iou5aLg+jhOk 0DXL9HyauxS1aqQysljUEw2kurMK3nYgbkfS0Nb8cQwMfp8bgnCpl/OY8g0qTRLyuIUMfbwbcj WZ9uhQNLwKFVqLK4Vq1X8sPESq1Vub/wV79XEZey3yfik637B7FQdGEyvyHnnDCAIopqlq1ScV k/csJktyg1opUjyzkdmJdjUv Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 14:24:46 -0700 IronPort-SDR: AxKl6PtRcmwE47v6682827tjnBH2iFfBkF1gI2iz7B7f2ehG1Wji6z7rCZUxD1n5B76/oHZh98 Zwgu5OgmFL8cvWNvh91jgvGPbIoKrbyNSi+sSTSFiaJ6c+rYYRRrRgk86ZCEQNGnHQRydx6ZF0 GoMNaHKUcYVabaMntdAafYTMHicyTBjzZWi11hBag6y8l5ckIIUApCw3BDFHgl1xb37PSF2Rb7 qTEXtZU6fw8U5P2OgQZwpiwbUCic7++vbVr5ybCm4viPSFyjORoaRZHMMbhijhIAMqwHDu17uS WUg= WDCIronportException: Internal Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2021 14:49:59 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4H9W2v1jdWz1Rwrx for ; Thu, 16 Sep 2021 14:49:59 -0700 (PDT) Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1631828998; x=1634420999; bh=bEGVNCgosMHtUlxH9k OtaXa5oZpBJ9IYzT/i1SohdGA=; b=nBHJFvkZYNuFccWzE8vNVHyjwnOBmg5xi5 DK1r9dzKOS1G/SU1FkSBzuML+53pSs/APiiIeVOBDNG38EpU5NhFipzGUvu6MYZ2 Zt/dJeCO8HWOU6gwGsOamo8qSz7ZlfA64J4LARX7pGxF3u3PixQR7CB4880asxzU 1ffy2PduFKIImGaBtCs/vvvA/e5tr8Dlf2ljUGyCPKo4Yc2UeTVu++ZQGRpOygEZ 0/PzuFA5mR68v4gnZxcchO69DKdbxW5q+WZcH/hTelryAbVK1TDMfCI2TErD1WJd w9MuEJ5PDgeahD2khduJXysOlarI7KQ5VOd4SOhCYVTsAp0G/GLQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id vteDRpENx0Ee for ; Thu, 16 Sep 2021 14:49:58 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.23]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4H9W2q20Vlz1RvlV; Thu, 16 Sep 2021 14:49:54 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Alistair Francis , Bin Meng Subject: [PULL 09/21] sifive_u: Connect the SiFive PWM device Date: Fri, 17 Sep 2021 07:48:52 +1000 Message-Id: <20210916214904.734206-10-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210916214904.734206-1-alistair.francis@opensource.wdc.com> References: <20210916214904.734206-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=886e160e1=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Connect the SiFive PWM device and expose it via the device tree. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alist= air.francis@wdc.com --- docs/system/riscv/sifive_u.rst | 1 + include/hw/riscv/sifive_u.h | 14 ++++++++- hw/riscv/sifive_u.c | 55 +++++++++++++++++++++++++++++++++- hw/riscv/Kconfig | 1 + 4 files changed, 69 insertions(+), 2 deletions(-) diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.= rst index 01108b5ecc..7c65e9c440 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -24,6 +24,7 @@ The ``sifive_u`` machine supports the following devices= : * 2 QSPI controllers * 1 ISSI 25WP256 flash * 1 SD card in SPI mode +* PWM0 and PWM1 =20 Please note the real world HiFive Unleashed board has a fixed configurat= ion of 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bi= t mode. diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2656b39808..f71c90c94c 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -27,6 +27,7 @@ #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" #include "hw/ssi/sifive_spi.h" +#include "hw/timer/sifive_pwm.h" =20 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState { SiFiveSPIState spi0; SiFiveSPIState spi2; CadenceGEMState gem; + SiFivePwmState pwm[2]; =20 uint32_t serial; char *cpu_type; @@ -92,7 +94,9 @@ enum { SIFIVE_U_DEV_FLASH0, SIFIVE_U_DEV_DRAM, SIFIVE_U_DEV_GEM, - SIFIVE_U_DEV_GEM_MGMT + SIFIVE_U_DEV_GEM_MGMT, + SIFIVE_U_DEV_PWM0, + SIFIVE_U_DEV_PWM1 }; =20 enum { @@ -126,6 +130,14 @@ enum { SIFIVE_U_PDMA_IRQ5 =3D 28, SIFIVE_U_PDMA_IRQ6 =3D 29, SIFIVE_U_PDMA_IRQ7 =3D 30, + SIFIVE_U_PWM0_IRQ0 =3D 42, + SIFIVE_U_PWM0_IRQ1 =3D 43, + SIFIVE_U_PWM0_IRQ2 =3D 44, + SIFIVE_U_PWM0_IRQ3 =3D 45, + SIFIVE_U_PWM1_IRQ0 =3D 46, + SIFIVE_U_PWM1_IRQ1 =3D 47, + SIFIVE_U_PWM1_IRQ2 =3D 48, + SIFIVE_U_PWM1_IRQ3 =3D 49, SIFIVE_U_QSPI0_IRQ =3D 51, SIFIVE_U_GEM_IRQ =3D 53 }; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6766edc1d0..f4cde10667 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -17,6 +17,7 @@ * 7) DMA (Direct Memory Access Controller) * 8) SPI0 connected to an SPI flash * 9) SPI2 connected to an SD card + * 10) PWM0 and PWM1 * * This board currently generates devicetree dynamically that indicates = at least * two harts and up to five harts. @@ -75,6 +76,8 @@ static const MemMapEntry sifive_u_memmap[] =3D { [SIFIVE_U_DEV_PRCI] =3D { 0x10000000, 0x1000 }, [SIFIVE_U_DEV_UART0] =3D { 0x10010000, 0x1000 }, [SIFIVE_U_DEV_UART1] =3D { 0x10011000, 0x1000 }, + [SIFIVE_U_DEV_PWM0] =3D { 0x10020000, 0x1000 }, + [SIFIVE_U_DEV_PWM1] =3D { 0x10021000, 0x1000 }, [SIFIVE_U_DEV_QSPI0] =3D { 0x10040000, 0x1000 }, [SIFIVE_U_DEV_QSPI2] =3D { 0x10050000, 0x1000 }, [SIFIVE_U_DEV_GPIO] =3D { 0x10060000, 0x1000 }, @@ -441,6 +444,38 @@ static void create_fdt(SiFiveUState *s, const MemMap= Entry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); =20 + nodename =3D g_strdup_printf("/soc/pwm@%lx", + (long)memmap[SIFIVE_U_DEV_PWM0].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_PWM0].base, + 0x0, memmap[SIFIVE_U_DEV_PWM0].size); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandl= e); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, + SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); + g_free(nodename); + + nodename =3D g_strdup_printf("/soc/pwm@%lx", + (long)memmap[SIFIVE_U_DEV_PWM1].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_PWM1].base, + 0x0, memmap[SIFIVE_U_DEV_PWM1].size); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandl= e); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, + SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); + g_free(nodename); + nodename =3D g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_DEV_UART1].base); qemu_fdt_add_subnode(fdt, nodename); @@ -765,6 +800,8 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); + object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); + object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); } =20 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -777,7 +814,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; - int i; + int i, j; NICInfo *nd =3D &nd_table[0]; =20 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus -= 1); @@ -904,6 +941,22 @@ static void sifive_u_soc_realize(DeviceState *dev, E= rror **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IR= Q)); =20 + /* PWM */ + for (i =3D 0; i < 2; i++) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, + memmap[SIFIVE_U_DEV_PWM0].base + (0x1000= * i)); + + /* Connect PWM interrupts to the PLIC */ + for (j =3D 0; j < SIFIVE_PWM_IRQS; j++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_U_PWM0_IRQ0 + (i * 4) + j= )); + } + } + create_unimplemented_device("riscv.sifive.u.gem-mgmt", memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT= ].size); =20 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index ff75add6f3..d56c339ef6 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -69,6 +69,7 @@ config SIFIVE_U select SIFIVE_UART select SIFIVE_U_OTP select SIFIVE_U_PRCI + select SIFIVE_PWM select SSI_M25P80 select SSI_SD select UNIMP --=20 2.31.1