From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Max Hsu <max.hsu@sifive.com>, Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions
Date: Fri, 17 Sep 2021 07:48:58 +1000 [thread overview]
Message-ID: <20210916214904.734206-16-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210916214904.734206-1-alistair.francis@opensource.wdc.com>
From: Frank Chang <frank.chang@sifive.com>
Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will be transferred.
The following result is PDMA tested in U-Boot on Unmatched board:
=> mw.l 0x3000000 0x0 <= Disclaim channel 0
(Channel 0 is not claimed)
=> mw.l 0x3000004 0x55000000 <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2 <= NextBytes = 2
=> mw.q 0x3000010 0x84000000 <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000 <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321 <= Fill test data to dst
=> mw.l 0x84001000 0x12345678 <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000 .......U........
03000010: 84000000 00000000 84001000 00000000 ................
=> mw.l 0x3000000 0x3 <= Set channel 0 run and claim bits
=> md.l 0x3000000 8 <= Dump PDMA status
03000000: 00000001 66000000 00000000 00000000 .......f........
03000010: 00000000 00000000 00000000 00000000 ................
=> md.l 0x84000000 1; md.l 0x84001000 1 <= Dump src/dst memory contents
84000000: 87654321 !Ce.
84001000: 12345678 xV4.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/dma/sifive_pdma.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
index d92e27dfdc..a8ce3e6699 100644
--- a/hw/dma/sifive_pdma.c
+++ b/hw/dma/sifive_pdma.c
@@ -252,6 +252,15 @@ static void sifive_pdma_write(void *opaque, hwaddr offset,
s->chan[ch].control = value;
+ /*
+ * If channel was not claimed before run bit is set,
+ * DMA won't run.
+ */
+ if (!claimed) {
+ s->chan[ch].control &= ~CONTROL_RUN;
+ return;
+ }
+
if (value & CONTROL_RUN) {
sifive_pdma_run(s, ch);
}
--
2.31.1
next prev parent reply other threads:[~2021-09-16 21:58 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-16 21:48 [PULL 00/21] riscv-to-apply queue Alistair Francis
2021-09-16 21:48 ` [PULL 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-16 21:48 ` [PULL 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-16 21:48 ` [PULL 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-16 21:48 ` [PULL 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-16 21:48 ` [PULL 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-16 21:48 ` [PULL 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-16 21:48 ` [PULL 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-16 21:48 ` [PULL 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-16 21:48 ` [PULL 09/21] sifive_u: Connect the SiFive PWM device Alistair Francis
2021-09-16 21:48 ` [PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-16 21:48 ` [PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-16 21:48 ` [PULL 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-16 21:48 ` [PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-16 21:48 ` [PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Alistair Francis
2021-09-16 21:48 ` Alistair Francis [this message]
2021-09-16 21:48 ` [PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-16 21:49 ` [PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-16 21:49 ` [PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions Alistair Francis
2021-09-16 21:49 ` [PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-16 21:49 ` [PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends Alistair Francis
2021-09-16 21:49 ` [PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-20 13:19 ` [PULL 00/21] riscv-to-apply queue Peter Maydell
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