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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 18/21] docs/system/riscv: sifive_u: Update U-Boot instructions
Date: Fri, 17 Sep 2021 07:49:01 +1000	[thread overview]
Message-ID: <20210916214904.734206-19-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20210916214904.734206-1-alistair.francis@opensource.wdc.com>

From: Bin Meng <bmeng.cn@gmail.com>

In U-Boot v2021.07 release, there were 2 major changes for the
SiFive Unleashed board support:

- Board config name was changed from sifive_fu540_defconfig to
  sifive_unleashed_defconfig
- The generic binman tool was used to generate the FIT image
  (combination of U-Boot proper, DTB and OpenSBI firmware)

which make the existing U-Boot instructions out of date.

Update the doc with latest instructions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911153431.10362-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/system/riscv/sifive_u.rst | 49 ++++++++++++++++++----------------
 1 file changed, 26 insertions(+), 23 deletions(-)

diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst
index 7c65e9c440..7b166567f9 100644
--- a/docs/system/riscv/sifive_u.rst
+++ b/docs/system/riscv/sifive_u.rst
@@ -210,15 +210,16 @@ command line options with ``qemu-system-riscv32``.
 Running U-Boot
 --------------
 
-U-Boot mainline v2021.01 release is tested at the time of writing. To build a
+U-Boot mainline v2021.07 release is tested at the time of writing. To build a
 U-Boot mainline bootloader that can be booted by the ``sifive_u`` machine, use
-the sifive_fu540_defconfig with similar commands as described above for Linux:
+the sifive_unleashed_defconfig with similar commands as described above for
+Linux:
 
 .. code-block:: bash
 
   $ export CROSS_COMPILE=riscv64-linux-
   $ export OPENSBI=/path/to/opensbi-riscv64-generic-fw_dynamic.bin
-  $ make sifive_fu540_defconfig
+  $ make sifive_unleashed_defconfig
 
 You will get spl/u-boot-spl.bin and u-boot.itb file in the build tree.
 
@@ -313,31 +314,29 @@ board on QEMU ``sifive_u`` machine out of the box. This allows users to
 develop and test the recommended RISC-V boot flow with a real world use
 case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
 then U-Boot SPL loads the combined payload image of OpenSBI fw_dynamic
-firmware and U-Boot proper. However sometimes we want to have a quick test
-of booting U-Boot on QEMU without the needs of preparing the SPI flash or
-SD card images, an alternate way can be used, which is to create a U-Boot
-S-mode image by modifying the configuration of U-Boot:
+firmware and U-Boot proper.
+
+However sometimes we want to have a quick test of booting U-Boot on QEMU
+without the needs of preparing the SPI flash or SD card images, an alternate
+way can be used, which is to create a U-Boot S-mode image by modifying the
+configuration of U-Boot:
 
 .. code-block:: bash
 
+  $ export CROSS_COMPILE=riscv64-linux-
+  $ make sifive_unleashed_defconfig
   $ make menuconfig
 
-then manually select the following configuration in U-Boot:
-
-  Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB
+then manually select the following configuration:
 
-This lets U-Boot to use the QEMU generated device tree blob. During the build,
-a build error will be seen below:
+  * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage bootloader DTB
 
-.. code-block:: none
+and unselect the following configuration:
 
-  MKIMAGE u-boot.img
-  ./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No such file or directory
-  ./tools/mkimage: failed to build FIT
-  make: *** [Makefile:1440: u-boot.img] Error 1
+  * Library routines ---> Allow access to binman information in the device tree
 
-The above errors can be safely ignored as we don't run U-Boot SPL under QEMU
-in this alternate configuration.
+This changes U-Boot to use the QEMU generated device tree blob, and bypass
+running the U-Boot SPL stage.
 
 Boot the 64-bit U-Boot S-mode image directly:
 
@@ -352,14 +351,18 @@ It's possible to create a 32-bit U-Boot S-mode image as well.
 .. code-block:: bash
 
   $ export CROSS_COMPILE=riscv64-linux-
-  $ make sifive_fu540_defconfig
+  $ make sifive_unleashed_defconfig
   $ make menuconfig
 
 then manually update the following configuration in U-Boot:
 
-  Device Tree Control > Provider of DTB for DT Control > Prior Stage bootloader DTB
-  RISC-V architecture > Base ISA > RV32I
-  Boot images > Text Base > 0x80400000
+  * Device Tree Control ---> Provider of DTB for DT Control ---> Prior Stage bootloader DTB
+  * RISC-V architecture ---> Base ISA ---> RV32I
+  * Boot options ---> Boot images ---> Text Base ---> 0x80400000
+
+and unselect the following configuration:
+
+  * Library routines ---> Allow access to binman information in the device tree
 
 Use the same command line options to boot the 32-bit U-Boot S-mode image:
 
-- 
2.31.1



  parent reply	other threads:[~2021-09-16 22:07 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-16 21:48 [PULL 00/21] riscv-to-apply queue Alistair Francis
2021-09-16 21:48 ` [PULL 01/21] target/riscv: Update the ePMP CSR address Alistair Francis
2021-09-16 21:48 ` [PULL 02/21] target/riscv: Fix satp write Alistair Francis
2021-09-16 21:48 ` [PULL 03/21] target/riscv: Expose interrupt pending bits as GPIO lines Alistair Francis
2021-09-16 21:48 ` [PULL 04/21] hw/intc: sifive_clint: Use RISC-V CPU " Alistair Francis
2021-09-16 21:48 ` [PULL 05/21] hw/intc: ibex_plic: Convert the PLIC to use " Alistair Francis
2021-09-16 21:48 ` [PULL 06/21] hw/intc: sifive_plic: " Alistair Francis
2021-09-16 21:48 ` [PULL 07/21] hw/intc: ibex_timer: Convert the timer " Alistair Francis
2021-09-16 21:48 ` [PULL 08/21] hw/timer: Add SiFive PWM support Alistair Francis
2021-09-16 21:48 ` [PULL 09/21] sifive_u: Connect the SiFive PWM device Alistair Francis
2021-09-16 21:48 ` [PULL 10/21] hw/intc: Rename sifive_clint sources to riscv_aclint sources Alistair Francis
2021-09-16 21:48 ` [PULL 11/21] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Alistair Francis
2021-09-16 21:48 ` [PULL 12/21] hw/riscv: virt: Re-factor FDT generation Alistair Francis
2021-09-16 21:48 ` [PULL 13/21] hw/riscv: virt: Add optional ACLINT support to virt machine Alistair Francis
2021-09-16 21:48 ` [PULL 14/21] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Alistair Francis
2021-09-16 21:48 ` [PULL 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Alistair Francis
2021-09-16 21:48 ` [PULL 16/21] hw/dma: sifive_pdma: allow non-multiple transaction size transactions Alistair Francis
2021-09-16 21:49 ` [PULL 17/21] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer Alistair Francis
2021-09-16 21:49 ` Alistair Francis [this message]
2021-09-16 21:49 ` [PULL 19/21] target/riscv: Backup/restore mstatus.SD bit when virtual register swapped Alistair Francis
2021-09-16 21:49 ` [PULL 20/21] target/riscv: csr: Rename HCOUNTEREN_CY and friends Alistair Francis
2021-09-16 21:49 ` [PULL 21/21] hw/riscv: opentitan: Correct the USB Dev address Alistair Francis
2021-09-20 13:19 ` [PULL 00/21] riscv-to-apply queue Peter Maydell

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