From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: WANG Xuerui <git@xen0n.name>
Subject: [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file
Date: Mon, 20 Sep 2021 16:04:24 +0800 [thread overview]
Message-ID: <20210920080451.408655-4-git@xen0n.name> (raw)
In-Reply-To: <20210920080451.408655-1-git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
create mode 100644 tcg/loongarch/tcg-target.h
diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h
new file mode 100644
index 0000000000..b5e70e01b5
--- /dev/null
+++ b/tcg/loongarch/tcg-target.h
@@ -0,0 +1,183 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
+ *
+ * Based on tcg/riscv/tcg-target.h
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef LOONGARCH_TCG_TARGET_H
+#define LOONGARCH_TCG_TARGET_H
+
+/*
+ * Loongson removed the (incomplete) 32-bit support from kernel and toolchain
+ * for the initial upstreaming of this architecture, so don't bother and just
+ * support the LP64 ABI for now.
+ */
+#if defined(__loongarch64)
+# define TCG_TARGET_REG_BITS 64
+#else
+# error unsupported LoongArch bitness
+#endif
+
+#define TCG_TARGET_INSN_UNIT_SIZE 4
+#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
+#define TCG_TARGET_NB_REGS 32
+#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
+
+typedef enum {
+ TCG_REG_ZERO,
+ TCG_REG_RA,
+ TCG_REG_TP,
+ TCG_REG_SP,
+ TCG_REG_A0,
+ TCG_REG_A1,
+ TCG_REG_A2,
+ TCG_REG_A3,
+ TCG_REG_A4,
+ TCG_REG_A5,
+ TCG_REG_A6,
+ TCG_REG_A7,
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+ TCG_REG_T4,
+ TCG_REG_T5,
+ TCG_REG_T6,
+ TCG_REG_T7,
+ TCG_REG_T8,
+ TCG_REG_RESERVED,
+ TCG_REG_S9,
+ TCG_REG_S0,
+ TCG_REG_S1,
+ TCG_REG_S2,
+ TCG_REG_S3,
+ TCG_REG_S4,
+ TCG_REG_S5,
+ TCG_REG_S6,
+ TCG_REG_S7,
+ TCG_REG_S8,
+
+ /* aliases */
+ TCG_AREG0 = TCG_REG_S0,
+ TCG_GUEST_BASE_REG = TCG_REG_S1,
+ TCG_REG_TMP0 = TCG_REG_T8,
+ TCG_REG_TMP1 = TCG_REG_T7,
+ TCG_REG_TMP2 = TCG_REG_T6,
+} TCGReg;
+
+/* used for function call generation */
+#define TCG_REG_CALL_STACK TCG_REG_SP
+#define TCG_TARGET_STACK_ALIGN 16
+#define TCG_TARGET_CALL_ALIGN_ARGS 1
+#define TCG_TARGET_CALL_STACK_OFFSET 0
+
+/* optional instructions */
+#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_div_i32 1
+#define TCG_TARGET_HAS_rem_i32 1
+#define TCG_TARGET_HAS_div2_i32 0
+#define TCG_TARGET_HAS_rot_i32 1
+#define TCG_TARGET_HAS_deposit_i32 1
+#define TCG_TARGET_HAS_extract_i32 1
+#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_extract2_i32 0
+#define TCG_TARGET_HAS_add2_i32 0
+#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_mulu2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muluh_i32 1
+#define TCG_TARGET_HAS_mulsh_i32 1
+#define TCG_TARGET_HAS_ext8s_i32 1
+#define TCG_TARGET_HAS_ext16s_i32 1
+#define TCG_TARGET_HAS_ext8u_i32 1
+#define TCG_TARGET_HAS_ext16u_i32 1
+#define TCG_TARGET_HAS_bswap16_i32 0
+#define TCG_TARGET_HAS_bswap32_i32 1
+#define TCG_TARGET_HAS_not_i32 1
+#define TCG_TARGET_HAS_neg_i32 1
+#define TCG_TARGET_HAS_andc_i32 1
+#define TCG_TARGET_HAS_orc_i32 1
+#define TCG_TARGET_HAS_eqv_i32 0
+#define TCG_TARGET_HAS_nand_i32 0
+#define TCG_TARGET_HAS_nor_i32 1
+#define TCG_TARGET_HAS_clz_i32 1
+#define TCG_TARGET_HAS_ctz_i32 1
+#define TCG_TARGET_HAS_ctpop_i32 0
+#define TCG_TARGET_HAS_direct_jump 0
+#define TCG_TARGET_HAS_brcond2 0
+#define TCG_TARGET_HAS_setcond2 0
+#define TCG_TARGET_HAS_qemu_st8_i32 0
+
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
+#define TCG_TARGET_HAS_div2_i64 0
+#define TCG_TARGET_HAS_rot_i64 1
+#define TCG_TARGET_HAS_deposit_i64 1
+#define TCG_TARGET_HAS_extract_i64 1
+#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extract2_i64 0
+#define TCG_TARGET_HAS_extrl_i64_i32 1
+#define TCG_TARGET_HAS_extrh_i64_i32 1
+#define TCG_TARGET_HAS_ext8s_i64 1
+#define TCG_TARGET_HAS_ext16s_i64 1
+#define TCG_TARGET_HAS_ext32s_i64 1
+#define TCG_TARGET_HAS_ext8u_i64 1
+#define TCG_TARGET_HAS_ext16u_i64 1
+#define TCG_TARGET_HAS_ext32u_i64 1
+#define TCG_TARGET_HAS_bswap16_i64 0
+#define TCG_TARGET_HAS_bswap32_i64 0
+#define TCG_TARGET_HAS_bswap64_i64 1
+#define TCG_TARGET_HAS_not_i64 1
+#define TCG_TARGET_HAS_neg_i64 1
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_orc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_nand_i64 0
+#define TCG_TARGET_HAS_nor_i64 1
+#define TCG_TARGET_HAS_clz_i64 1
+#define TCG_TARGET_HAS_ctz_i64 1
+#define TCG_TARGET_HAS_ctpop_i64 0
+#define TCG_TARGET_HAS_add2_i64 0
+#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_muls2_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
+#endif
+
+/* not defined -- call should be eliminated at compile time */
+void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
+
+#define TCG_TARGET_DEFAULT_MO (0)
+
+#ifdef CONFIG_SOFTMMU
+#define TCG_TARGET_NEED_LDST_LABELS
+#endif
+
+#define TCG_TARGET_HAS_MEMORY_BSWAP 0
+
+#endif /* LOONGARCH_TCG_TARGET_H */
--
2.33.0
next prev parent reply other threads:[~2021-09-20 14:13 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 8:04 [PATCH 00/30] 64-bit LoongArch port of QEMU TCG WANG Xuerui
2021-09-20 8:04 ` [PATCH 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-20 8:04 ` [PATCH 02/30] MAINTAINERS: Add tcg/loongarch entry with myself as maintainer WANG Xuerui
2021-09-20 14:50 ` Richard Henderson
2021-09-20 8:04 ` WANG Xuerui [this message]
2021-09-20 14:23 ` [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file Richard Henderson
2021-09-20 16:20 ` WANG Xuerui
2021-09-20 16:25 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-20 15:55 ` Richard Henderson
2021-09-20 16:24 ` WANG Xuerui
2021-09-21 9:58 ` Philippe Mathieu-Daudé
2021-09-21 11:40 ` WANG Xuerui
2021-09-20 8:04 ` [PATCH 05/30] tcg/loongarch: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-20 15:57 ` Richard Henderson
2021-09-20 16:27 ` WANG Xuerui
2021-09-20 8:04 ` [PATCH 06/30] tcg/loongarch: Define the operand constraints WANG Xuerui
2021-09-20 14:28 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 07/30] tcg/loongarch: Implement necessary relocation operations WANG Xuerui
2021-09-20 14:36 ` Richard Henderson
2021-09-20 17:15 ` WANG Xuerui
2021-09-20 8:04 ` [PATCH 08/30] tcg/loongarch: Implement the memory barrier op WANG Xuerui
2021-09-20 8:04 ` [PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-20 14:47 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 10/30] tcg/loongarch: Implement goto_ptr WANG Xuerui
2021-09-20 14:49 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops WANG Xuerui
2021-09-20 14:50 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-20 14:54 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 13/30] tcg/loongarch: Implement deposit/extract ops WANG Xuerui
2021-09-20 14:55 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64 WANG Xuerui
2021-09-20 15:11 ` Richard Henderson
2021-09-20 18:20 ` Richard Henderson
2021-09-21 6:37 ` WANG Xuerui
2021-09-20 8:04 ` [PATCH 15/30] tcg/loongarch: Implement clz/ctz ops WANG Xuerui
2021-09-20 16:10 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 16/30] tcg/loongarch: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-20 16:13 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops WANG Xuerui
2021-09-20 16:16 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-20 16:16 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 19/30] tcg/loongarch: Implement br/brcond ops WANG Xuerui
2021-09-20 16:20 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 20/30] tcg/loongarch: Implement setcond ops WANG Xuerui
2021-09-20 16:24 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 21/30] tcg/loongarch: Implement tcg_out_call WANG Xuerui
2021-09-20 16:31 ` Richard Henderson
2021-09-20 16:35 ` Richard Henderson
2021-09-21 6:42 ` WANG Xuerui
2021-09-20 8:04 ` [PATCH 22/30] tcg/loongarch: Implement simple load/store ops WANG Xuerui
2021-09-20 16:35 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 23/30] tcg/loongarch: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-20 17:10 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-20 17:15 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 25/30] tcg/loongarch: Implement exit_tb/goto_tb WANG Xuerui
2021-09-20 17:16 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 26/30] tcg/loongarch: Implement tcg_target_init WANG Xuerui
2021-09-20 17:19 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 27/30] tcg/loongarch: Register the JIT WANG Xuerui
2021-09-20 17:21 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts WANG Xuerui
2021-09-20 17:23 ` Richard Henderson
2021-09-21 6:02 ` WANG Xuerui
2021-09-21 6:59 ` Philippe Mathieu-Daudé
2021-09-21 7:24 ` WANG Xuerui
2021-09-21 13:30 ` Richard Henderson
2021-09-21 14:07 ` WANG Xuerui
2021-09-21 14:10 ` WANG Xuerui
2021-09-21 14:42 ` Peter Maydell
2021-09-21 15:59 ` Richard Henderson
2021-09-21 16:09 ` WANG Xuerui
2021-09-21 17:26 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 29/30] linux-user: Add host dependency for 64-bit LoongArch WANG Xuerui
2021-09-20 17:26 ` Richard Henderson
2021-09-20 8:04 ` [PATCH 30/30] accel/tcg/user-exec: Implement CPU-specific signal handler for LoongArch hosts WANG Xuerui
2021-09-20 17:31 ` Richard Henderson
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