From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/27] hw/intc: Set GIC maintenance interrupt level to only 0 or 1
Date: Mon, 20 Sep 2021 15:19:26 +0100 [thread overview]
Message-ID: <20210920141947.5537-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org>
From: Shashi Mallela <shashi.mallela@linaro.org>
During sbsa acs level 3 testing, it is seen that the GIC maintenance
interrupts are not triggered and the related test cases fail. This
is because we were incorrectly passing the value of the MISR register
(from maintenance_interrupt_state()) to qemu_set_irq() as the level
argument, whereas the device on the other end of this irq line
expects a 0/1 value.
Fix the logic to pass a 0/1 level indication, rather than a
0/not-0 value.
Fixes: c5fc89b36c0 ("hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()")
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210915205809.59068-1-shashi.mallela@linaro.org
[PMM: tweaked commit message; collapsed nested if()s into one]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 462a35f66eb..3fe5de8ad7d 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -417,8 +417,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
}
}
- if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
- maintlevel = maintenance_interrupt_state(cs);
+ if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) &&
+ maintenance_interrupt_state(cs) != 0) {
+ maintlevel = 1;
}
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
--
2.20.1
next prev parent reply other threads:[~2021-09-20 14:39 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 14:19 [PULL 00/27] target-arm queue Peter Maydell
2021-09-20 14:19 ` [PULL 01/27] elf2dmp: Check curl_easy_setopt() return value Peter Maydell
2021-09-20 14:19 ` [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size Peter Maydell
2021-09-20 14:19 ` [PULL 03/27] target/arm: Don't skip M-profile reset entirely in user mode Peter Maydell
2021-09-20 14:19 ` [PULL 04/27] target/arm: Always clear exclusive monitor on reset Peter Maydell
2021-09-20 14:19 ` [PULL 05/27] target/arm: Consolidate ifdef blocks in reset Peter Maydell
2021-09-20 14:19 ` Peter Maydell [this message]
2021-09-20 14:19 ` [PULL 07/27] arm: Move PMC register definitions to internals.h Peter Maydell
2021-09-20 14:19 ` [PULL 08/27] hvf: Add execute to dirty log permission bitmap Peter Maydell
2021-09-20 14:19 ` [PULL 09/27] hvf: Introduce hvf_arch_init() callback Peter Maydell
2021-09-20 14:19 ` [PULL 10/27] hvf: Add Apple Silicon support Peter Maydell
2021-09-20 14:19 ` [PULL 11/27] arm/hvf: Add a WFI handler Peter Maydell
2021-09-20 14:19 ` [PULL 12/27] hvf: arm: Implement -cpu host Peter Maydell
2021-09-20 14:19 ` [PULL 13/27] hvf: arm: Implement PSCI handling Peter Maydell
2021-09-20 14:19 ` [PULL 14/27] arm: Add Hypervisor.framework build target Peter Maydell
2021-09-20 14:19 ` [PULL 15/27] hvf: arm: Add rudimentary PMC support Peter Maydell
2021-09-20 14:19 ` [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop Peter Maydell
2021-09-20 14:19 ` [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration Peter Maydell
2021-09-20 14:19 ` [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-20 14:19 ` [PULL 19/27] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-20 14:19 ` [PULL 20/27] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-20 14:19 ` [PULL 21/27] target/arm: Optimize MVE VNEG, VABS Peter Maydell
2021-09-20 14:19 ` [PULL 22/27] target/arm: Optimize MVE VDUP Peter Maydell
2021-09-20 14:19 ` [PULL 23/27] target/arm: Optimize MVE VMVN Peter Maydell
2021-09-20 14:19 ` [PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms Peter Maydell
2021-09-20 14:19 ` [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL Peter Maydell
2021-09-20 14:19 ` [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI Peter Maydell
2021-09-20 14:19 ` [PULL 27/27] target/arm: Optimize MVE 1op-immediate insns Peter Maydell
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