From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/27] arm: Move PMC register definitions to internals.h
Date: Mon, 20 Sep 2021 15:19:27 +0100 [thread overview]
Message-ID: <20210920141947.5537-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org>
From: Alexander Graf <agraf@csgraf.de>
We will need PMC register definitions in accel specific code later.
Move all constant definitions to common arm headers so we can reuse
them.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210916155404.86958-2-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++
target/arm/helper.c | 44 ------------------------------------------
2 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index cd2ea8a3883..777f9687648 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1226,4 +1226,48 @@ enum MVEECIState {
/* All other values reserved */
};
+/* Definitions for the PMU registers */
+#define PMCRN_MASK 0xf800
+#define PMCRN_SHIFT 11
+#define PMCRLC 0x40
+#define PMCRDP 0x20
+#define PMCRX 0x10
+#define PMCRD 0x8
+#define PMCRC 0x4
+#define PMCRP 0x2
+#define PMCRE 0x1
+/*
+ * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
+ * which can be written as 1 to trigger behaviour but which stay RAZ).
+ */
+#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
+
+#define PMXEVTYPER_P 0x80000000
+#define PMXEVTYPER_U 0x40000000
+#define PMXEVTYPER_NSK 0x20000000
+#define PMXEVTYPER_NSU 0x10000000
+#define PMXEVTYPER_NSH 0x08000000
+#define PMXEVTYPER_M 0x04000000
+#define PMXEVTYPER_MT 0x02000000
+#define PMXEVTYPER_EVTCOUNT 0x0000ffff
+#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
+ PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
+ PMXEVTYPER_M | PMXEVTYPER_MT | \
+ PMXEVTYPER_EVTCOUNT)
+
+#define PMCCFILTR 0xf8000000
+#define PMCCFILTR_M PMXEVTYPER_M
+#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
+
+static inline uint32_t pmu_num_counters(CPUARMState *env)
+{
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
+}
+
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+static inline uint64_t pmu_counter_mask(CPUARMState *env)
+{
+ return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
+}
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b210da2bc26..21ee94ec2e7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1114,50 +1114,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
REGINFO_SENTINEL
};
-/* Definitions for the PMU registers */
-#define PMCRN_MASK 0xf800
-#define PMCRN_SHIFT 11
-#define PMCRLC 0x40
-#define PMCRDP 0x20
-#define PMCRX 0x10
-#define PMCRD 0x8
-#define PMCRC 0x4
-#define PMCRP 0x2
-#define PMCRE 0x1
-/*
- * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
- * which can be written as 1 to trigger behaviour but which stay RAZ).
- */
-#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
-
-#define PMXEVTYPER_P 0x80000000
-#define PMXEVTYPER_U 0x40000000
-#define PMXEVTYPER_NSK 0x20000000
-#define PMXEVTYPER_NSU 0x10000000
-#define PMXEVTYPER_NSH 0x08000000
-#define PMXEVTYPER_M 0x04000000
-#define PMXEVTYPER_MT 0x02000000
-#define PMXEVTYPER_EVTCOUNT 0x0000ffff
-#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
- PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
- PMXEVTYPER_M | PMXEVTYPER_MT | \
- PMXEVTYPER_EVTCOUNT)
-
-#define PMCCFILTR 0xf8000000
-#define PMCCFILTR_M PMXEVTYPER_M
-#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
-
-static inline uint32_t pmu_num_counters(CPUARMState *env)
-{
- return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
-}
-
-/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
-static inline uint64_t pmu_counter_mask(CPUARMState *env)
-{
- return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
-}
-
typedef struct pm_event {
uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
/* If the event is supported on this CPU (used to generate PMCEID[01]) */
--
2.20.1
next prev parent reply other threads:[~2021-09-20 14:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 14:19 [PULL 00/27] target-arm queue Peter Maydell
2021-09-20 14:19 ` [PULL 01/27] elf2dmp: Check curl_easy_setopt() return value Peter Maydell
2021-09-20 14:19 ` [PULL 02/27] elf2dmp: Fail cleanly if PDB file specifies zero block_size Peter Maydell
2021-09-20 14:19 ` [PULL 03/27] target/arm: Don't skip M-profile reset entirely in user mode Peter Maydell
2021-09-20 14:19 ` [PULL 04/27] target/arm: Always clear exclusive monitor on reset Peter Maydell
2021-09-20 14:19 ` [PULL 05/27] target/arm: Consolidate ifdef blocks in reset Peter Maydell
2021-09-20 14:19 ` [PULL 06/27] hw/intc: Set GIC maintenance interrupt level to only 0 or 1 Peter Maydell
2021-09-20 14:19 ` Peter Maydell [this message]
2021-09-20 14:19 ` [PULL 08/27] hvf: Add execute to dirty log permission bitmap Peter Maydell
2021-09-20 14:19 ` [PULL 09/27] hvf: Introduce hvf_arch_init() callback Peter Maydell
2021-09-20 14:19 ` [PULL 10/27] hvf: Add Apple Silicon support Peter Maydell
2021-09-20 14:19 ` [PULL 11/27] arm/hvf: Add a WFI handler Peter Maydell
2021-09-20 14:19 ` [PULL 12/27] hvf: arm: Implement -cpu host Peter Maydell
2021-09-20 14:19 ` [PULL 13/27] hvf: arm: Implement PSCI handling Peter Maydell
2021-09-20 14:19 ` [PULL 14/27] arm: Add Hypervisor.framework build target Peter Maydell
2021-09-20 14:19 ` [PULL 15/27] hvf: arm: Add rudimentary PMC support Peter Maydell
2021-09-20 14:19 ` [PULL 16/27] target/arm: Avoid goto_tb if we're trying to exit to the main loop Peter Maydell
2021-09-20 14:19 ` [PULL 17/27] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration Peter Maydell
2021-09-20 14:19 ` [PULL 18/27] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-20 14:19 ` [PULL 19/27] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-20 14:19 ` [PULL 20/27] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-20 14:19 ` [PULL 21/27] target/arm: Optimize MVE VNEG, VABS Peter Maydell
2021-09-20 14:19 ` [PULL 22/27] target/arm: Optimize MVE VDUP Peter Maydell
2021-09-20 14:19 ` [PULL 23/27] target/arm: Optimize MVE VMVN Peter Maydell
2021-09-20 14:19 ` [PULL 24/27] target/arm: Optimize MVE VSHL, VSHR immediate forms Peter Maydell
2021-09-20 14:19 ` [PULL 25/27] target/arm: Optimize MVE VSHLL and VMOVL Peter Maydell
2021-09-20 14:19 ` [PULL 26/27] target/arm: Optimize MVE VSLI and VSRI Peter Maydell
2021-09-20 14:19 ` [PULL 27/27] target/arm: Optimize MVE 1op-immediate insns Peter Maydell
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