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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n17sm16229693wrp.17.2021.09.20.07.19.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 07:19:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/27] arm: Move PMC register definitions to internals.h Date: Mon, 20 Sep 2021 15:19:27 +0100 Message-Id: <20210920141947.5537-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210920141947.5537-1-peter.maydell@linaro.org> References: <20210920141947.5537-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alexander Graf We will need PMC register definitions in accel specific code later. Move all constant definitions to common arm headers so we can reuse them. Signed-off-by: Alexander Graf Reviewed-by: Peter Maydell Message-id: 20210916155404.86958-2-agraf@csgraf.de Signed-off-by: Peter Maydell --- target/arm/internals.h | 44 ++++++++++++++++++++++++++++++++++++++++++ target/arm/helper.c | 44 ------------------------------------------ 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index cd2ea8a3883..777f9687648 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1226,4 +1226,48 @@ enum MVEECIState { /* All other values reserved */ }; +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRLC 0x40 +#define PMCRDP 0x20 +#define PMCRX 0x10 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRP 0x2 +#define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) + +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + +static inline uint32_t pmu_num_counters(CPUARMState *env) +{ + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; +} + +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +static inline uint64_t pmu_counter_mask(CPUARMState *env) +{ + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); +} + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index b210da2bc26..21ee94ec2e7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1114,50 +1114,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { REGINFO_SENTINEL }; -/* Definitions for the PMU registers */ -#define PMCRN_MASK 0xf800 -#define PMCRN_SHIFT 11 -#define PMCRLC 0x40 -#define PMCRDP 0x20 -#define PMCRX 0x10 -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRP 0x2 -#define PMCRE 0x1 -/* - * Mask of PMCR bits writeable by guest (not including WO bits like C, P, - * which can be written as 1 to trigger behaviour but which stay RAZ). - */ -#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) - -#define PMXEVTYPER_P 0x80000000 -#define PMXEVTYPER_U 0x40000000 -#define PMXEVTYPER_NSK 0x20000000 -#define PMXEVTYPER_NSU 0x10000000 -#define PMXEVTYPER_NSH 0x08000000 -#define PMXEVTYPER_M 0x04000000 -#define PMXEVTYPER_MT 0x02000000 -#define PMXEVTYPER_EVTCOUNT 0x0000ffff -#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \ - PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ - PMXEVTYPER_M | PMXEVTYPER_MT | \ - PMXEVTYPER_EVTCOUNT) - -#define PMCCFILTR 0xf8000000 -#define PMCCFILTR_M PMXEVTYPER_M -#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) - -static inline uint32_t pmu_num_counters(CPUARMState *env) -{ - return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; -} - -/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ -static inline uint64_t pmu_counter_mask(CPUARMState *env) -{ - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); -} - typedef struct pm_event { uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ /* If the event is supported on this CPU (used to generate PMCEID[01]) */ -- 2.20.1