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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id f19sm702529wmf.11.2021.09.20.14.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Sep 2021 14:44:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v5 01/31] target/arm: Implement arm_v7m_cpu_has_work() Date: Mon, 20 Sep 2021 23:44:17 +0200 Message-Id: <20210920214447.2998623-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210920214447.2998623-1-f4bug@amsat.org> References: <20210920214447.2998623-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Michael Davidsaver , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Implement SysemuCPUOps::has_work() handler for the ARM v7M CPU. See the comments added in commit 7ecdaa4a963 ("armv7m: Fix condition check for taking exceptions") which eventually forgot to implement this has_work() handler: * ARMv7-M interrupt masking works differently than -A or -R. * There is no FIQ/IRQ distinction. The NVIC signal any pending interrupt by raising ARM_CPU_IRQ (see commit 56b7c66f498: "armv7m: QOMify the armv7m container") which ends setting the CPU_INTERRUPT_HARD bit in interrupt_request. Thus arm_v7m_cpu_has_work() implementation is thus quite trivial, we simply need to check for this bit. Cc: Peter Maydell Cc: Michael Davidsaver Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu_tcg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0d5adccf1a7..da348938407 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -23,6 +23,11 @@ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +static bool arm_v7m_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & CPU_INTERRUPT_HARD; +} + static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc = CPU_GET_CLASS(cs); @@ -920,6 +925,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data) acc->info = data; #ifdef CONFIG_TCG + cc->has_work = arm_v7m_cpu_has_work; cc->tcg_ops = &arm_v7m_tcg_ops; #endif /* CONFIG_TCG */ -- 2.31.1