From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 10/10] tcg/riscv: Remove add with zero on user-only memory access
Date: Mon, 20 Sep 2021 19:25:34 -0700 [thread overview]
Message-ID: <20210921022534.365291-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.c.inc | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c16f96b401..dc8d8f1de2 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1130,10 +1130,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
-
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
+ if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
@@ -1199,10 +1196,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
-
- if (guest_base == 0) {
- tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
- } else {
+ if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
--
2.25.1
prev parent reply other threads:[~2021-09-21 2:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 2:25 [PULL 00/10] tcg patch queue, v2 Richard Henderson
2021-09-21 2:25 ` [PULL 01/10] include/exec: Move cpu_signal_handler declaration Richard Henderson
2021-09-21 2:25 ` [PULL 02/10] accel/tcg: Restrict cpu_handle_halt() to sysemu Richard Henderson
2021-09-21 2:25 ` [PULL 03/10] tcg/mips: Drop inline markers Richard Henderson
2021-09-21 2:25 ` [PULL 04/10] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Richard Henderson
2021-09-21 2:25 ` [PULL 05/10] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Richard Henderson
2021-09-21 2:25 ` [PULL 06/10] tcg/mips: Drop special alignment for code_gen_buffer Richard Henderson
2021-09-21 2:25 ` [PULL 07/10] tcg/sparc: Drop inline markers Richard Henderson
2021-09-21 2:25 ` [PULL 08/10] tcg/sparc: Introduce tcg_out_mov_delay Richard Henderson
2021-09-21 2:25 ` [PULL 09/10] hw/core: Make do_unaligned_access noreturn Richard Henderson
2021-09-21 2:25 ` Richard Henderson [this message]
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