From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 02/10] accel/tcg: Restrict cpu_handle_halt() to sysemu
Date: Mon, 20 Sep 2021 19:25:26 -0700 [thread overview]
Message-ID: <20210921022534.365291-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210921022534.365291-1-richard.henderson@linaro.org>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit 372579427a5 ("tcg: enable thread-per-vCPU") added the following
comment describing EXCP_HALTED in qemu_tcg_cpu_thread_fn():
case EXCP_HALTED:
/* during start-up the vCPU is reset and the thread is
* kicked several times. If we don't ensure we go back
* to sleep in the halted state we won't cleanly
* start-up when the vCPU is enabled.
*
* cpu->halted should ensure we sleep in wait_io_event
*/
g_assert(cpu->halted);
break;
qemu_wait_io_event() is sysemu-specific, so we can restrict the
cpu_handle_halt() call in cpu_exec() to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210912172731.789788-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 75dbc1e4e3..5fd1ed3422 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -588,8 +588,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
static inline bool cpu_handle_halt(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
if (cpu->halted) {
-#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
+#if defined(TARGET_I386)
if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
X86CPU *x86_cpu = X86_CPU(cpu);
qemu_mutex_lock_iothread();
@@ -597,13 +598,14 @@ static inline bool cpu_handle_halt(CPUState *cpu)
cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
qemu_mutex_unlock_iothread();
}
-#endif
+#endif /* TARGET_I386 */
if (!cpu_has_work(cpu)) {
return true;
}
cpu->halted = 0;
}
+#endif /* !CONFIG_USER_ONLY */
return false;
}
--
2.25.1
next prev parent reply other threads:[~2021-09-21 2:27 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 2:25 [PULL 00/10] tcg patch queue, v2 Richard Henderson
2021-09-21 2:25 ` [PULL 01/10] include/exec: Move cpu_signal_handler declaration Richard Henderson
2021-09-21 2:25 ` Richard Henderson [this message]
2021-09-21 2:25 ` [PULL 03/10] tcg/mips: Drop inline markers Richard Henderson
2021-09-21 2:25 ` [PULL 04/10] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Richard Henderson
2021-09-21 2:25 ` [PULL 05/10] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Richard Henderson
2021-09-21 2:25 ` [PULL 06/10] tcg/mips: Drop special alignment for code_gen_buffer Richard Henderson
2021-09-21 2:25 ` [PULL 07/10] tcg/sparc: Drop inline markers Richard Henderson
2021-09-21 2:25 ` [PULL 08/10] tcg/sparc: Introduce tcg_out_mov_delay Richard Henderson
2021-09-21 2:25 ` [PULL 09/10] hw/core: Make do_unaligned_access noreturn Richard Henderson
2021-09-21 2:25 ` [PULL 10/10] tcg/riscv: Remove add with zero on user-only memory access Richard Henderson
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