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Mon, 20 Sep 2021 23:55:50 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.26]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HDByn3t1gz1RvlH; Mon, 20 Sep 2021 23:55:44 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Frank Chang , Max Hsu , Bin Meng , Alistair Francis Subject: [PULL v2 15/21] hw/dma: sifive_pdma: claim bit must be set before DMA transactions Date: Tue, 21 Sep 2021 16:54:06 +1000 Message-Id: <20210921065412.312381-16-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> References: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=891501f09=alistair.francis@opensource.wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Real PDMA must have Control.claim bit to be set before Control.run bit is set to start any DMA transactions. Otherwise nothing will be transferred. The following result is PDMA tested in U-Boot on Unmatched board: =3D> mw.l 0x3000000 0x0 <=3D Disclaim channel 0 (Channel 0 is not claimed) =3D> mw.l 0x3000004 0x55000000 <=3D wsize =3D rsize =3D 5 (= 2^5 =3D 32 bytes) =3D> mw.q 0x3000008 0x2 <=3D NextBytes =3D 2 =3D> mw.q 0x3000010 0x84000000 <=3D NextDestination =3D 0x8= 4000000 =3D> mw.q 0x3000018 0x84001000 <=3D NextSource =3D 0x840010= 00 =3D> mw.l 0x84000000 0x87654321 <=3D Fill test data to dst =3D> mw.l 0x84001000 0x12345678 <=3D Fill test data to src =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 00000000 55000000 00000002 00000000 .......U........ 03000010: 84000000 00000000 84001000 00000000 ................ =3D> mw.l 0x3000000 0x3 <=3D Set channel 0 run and c= laim bits =3D> md.l 0x3000000 8 <=3D Dump PDMA status 03000000: 00000001 66000000 00000000 00000000 .......f........ 03000010: 00000000 00000000 00000000 00000000 ................ =3D> md.l 0x84000000 1; md.l 0x84001000 1 <=3D Dump src/dst memory con= tents 84000000: 87654321 !Ce. 84001000: 12345678 xV4. Signed-off-by: Frank Chang Tested-by: Max Hsu Reviewed-by: Bin Meng Tested-by: Bin Meng Message-id: 20210912130553.179501-3-frank.chang@sifive.com Signed-off-by: Alistair Francis --- hw/dma/sifive_pdma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index d92e27dfdc..a8ce3e6699 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -252,6 +252,15 @@ static void sifive_pdma_write(void *opaque, hwaddr o= ffset, =20 s->chan[ch].control =3D value; =20 + /* + * If channel was not claimed before run bit is set, + * DMA won't run. + */ + if (!claimed) { + s->chan[ch].control &=3D ~CONTROL_RUN; + return; + } + if (value & CONTROL_RUN) { sifive_pdma_run(s, ch); } --=20 2.31.1