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Mon, 20 Sep 2021 23:55:03 -0700 (PDT) Received: from toolbox.alistair23.me (unknown [10.225.165.26]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HDBxt6wKZz1RvlH; Mon, 20 Sep 2021 23:54:58 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL v2 07/21] hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines Date: Tue, 21 Sep 2021 16:53:58 +1000 Message-Id: <20210921065412.312381-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> References: <20210921065412.312381-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=891501f09=alistair.francis@opensource.wdc.com; helo=esa3.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alist= air.francis@wdc.com --- include/hw/timer/ibex_timer.h | 2 ++ hw/riscv/opentitan.c | 3 +++ hw/timer/ibex_timer.c | 17 ++++++++++++----- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/include/hw/timer/ibex_timer.h b/include/hw/timer/ibex_timer.= h index 6a43537003..b6f69b38ee 100644 --- a/include/hw/timer/ibex_timer.h +++ b/include/hw/timer/ibex_timer.h @@ -48,5 +48,7 @@ struct IbexTimerState { uint32_t timebase_freq; =20 qemu_irq irq; + + qemu_irq m_timer_irq; }; #endif /* HW_IBEX_TIMER_H */ diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 048aced0ec..f7cfcf1c3a 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -183,6 +183,9 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev= _soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0, qdev_get_gpio_in(DEVICE(&s->plic), IBEX_TIMER_TIMEREXPIRED0_0)); + qdev_connect_gpio_out(DEVICE(&s->timer), 0, + qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), + IRQ_M_TIMER)); =20 create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 5befb53506..66e1f8e48c 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -77,7 +77,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s) /* * If the mtimecmp was in the past raise the interrupt now. */ - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + qemu_irq_raise(s->m_timer_irq); if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; qemu_set_irq(s->irq, true); @@ -86,7 +86,7 @@ static void ibex_timer_update_irqs(IbexTimerState *s) } =20 /* Setup a timer to trigger the interrupt in the future */ - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0)); + qemu_irq_lower(s->m_timer_irq); qemu_set_irq(s->irq, false); =20 diff =3D cpu->env.timecmp - now; @@ -106,10 +106,8 @@ static void ibex_timer_update_irqs(IbexTimerState *s= ) static void ibex_timer_cb(void *opaque) { IbexTimerState *s =3D opaque; - CPUState *cs =3D qemu_get_cpu(0); - RISCVCPU *cpu =3D RISCV_CPU(cs); =20 - riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1)); + qemu_irq_raise(s->m_timer_irq); if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) { s->timer_intr_state |=3D R_INTR_STATE_IS_0_MASK; qemu_set_irq(s->irq, true); @@ -280,12 +278,21 @@ static void ibex_timer_init(Object *obj) sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 +static void ibex_timer_realize(DeviceState *dev, Error **errp) +{ + IbexTimerState *s =3D IBEX_TIMER(dev); + + qdev_init_gpio_out(dev, &s->m_timer_irq, 1); +} + + static void ibex_timer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->reset =3D ibex_timer_reset; dc->vmsd =3D &vmstate_ibex_timer; + dc->realize =3D ibex_timer_realize; device_class_set_props(dc, ibex_timer_properties); } =20 --=20 2.31.1