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[83.35.24.118]) by smtp.gmail.com with ESMTPSA id c9sm5920723wmb.41.2021.09.24.02.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Sep 2021 02:41:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v6 31/40] target/riscv: Restrict has_work() handler to sysemu and TCG Date: Fri, 24 Sep 2021 11:38:38 +0200 Message-Id: <20210924093847.1014331-32-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210924093847.1014331-1-f4bug@amsat.org> References: <20210924093847.1014331-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V TCG CPUs" , Bin Meng , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Restrict has_work() to TCG sysemu. Reviewed-by: Richard Henderson Acked-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7c626d89cd7..ca76bc34d9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -335,9 +335,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, env->pc = tb->pc; } +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) static bool riscv_cpu_has_work(CPUState *cs) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; /* @@ -345,10 +345,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return (env->mip & env->mie) != 0; -#else - return true; -#endif } +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, target_ulong *data) @@ -678,6 +676,7 @@ static const struct TCGCPUOps riscv_tcg_ops = { .tlb_fill = riscv_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY + .has_work = riscv_cpu_has_work, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, .do_interrupt = riscv_cpu_do_interrupt, .do_transaction_failed = riscv_cpu_do_transaction_failed, @@ -697,7 +696,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; - cc->has_work = riscv_cpu_has_work; cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->gdb_read_register = riscv_cpu_gdb_read_register; -- 2.31.1