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From: WANG Xuerui <git@xen0n.name>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"XiaoJuan Yang" <yangxiaojuan@loongson.cn>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Song Gao" <gaosong@loongson.cn>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"WANG Xuerui" <git@xen0n.name>,
	"Laurent Vivier" <laurent@vivier.eu>
Subject: [PATCH v6 06/30] tcg/loongarch64: Define the operand constraints
Date: Sun, 26 Sep 2021 01:30:08 +0800	[thread overview]
Message-ID: <20210925173032.2434906-7-git@xen0n.name> (raw)
In-Reply-To: <20210925173032.2434906-1-git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 tcg/loongarch64/tcg-target-con-str.h | 28 +++++++++++++++
 tcg/loongarch64/tcg-target.c.inc     | 52 ++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)
 create mode 100644 tcg/loongarch64/tcg-target-con-str.h

diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h
new file mode 100644
index 0000000000..c3986a4fd4
--- /dev/null
+++ b/tcg/loongarch64/tcg-target-con-str.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define LoongArch target-specific operand constraints.
+ *
+ * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
+ *
+ * Based on tcg/riscv/tcg-target-con-str.h
+ *
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S12)
+CONST('N', TCG_CT_CONST_N12)
+CONST('U', TCG_CT_CONST_U12)
+CONST('Z', TCG_CT_CONST_ZERO)
+CONST('C', TCG_CT_CONST_C12)
+CONST('W', TCG_CT_CONST_WSZ)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 42eebef78e..64e57bd055 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -116,3 +116,55 @@ static const int tcg_target_call_oarg_regs[] = {
     TCG_REG_A0,
     TCG_REG_A1,
 };
+
+#define TCG_CT_CONST_ZERO  0x100
+#define TCG_CT_CONST_S12   0x200
+#define TCG_CT_CONST_N12   0x400
+#define TCG_CT_CONST_U12   0x800
+#define TCG_CT_CONST_C12   0x1000
+#define TCG_CT_CONST_WSZ   0x2000
+
+#define ALL_GENERAL_REGS      MAKE_64BIT_MASK(0, 32)
+/*
+ * For softmmu, we need to avoid conflicts with the first 5
+ * argument registers to call the helper.  Some of these are
+ * also used for the tlb lookup.
+ */
+#ifdef CONFIG_SOFTMMU
+#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
+#else
+#define SOFTMMU_RESERVE_REGS  0
+#endif
+
+
+static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
+{
+    return sextract64(val, pos, len);
+}
+
+/* test if a constant matches the constraint */
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+{
+    if (ct & TCG_CT_CONST) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
+        return true;
+    }
+    if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
+        return true;
+    }
+    return false;
+}
-- 
2.33.0



  parent reply	other threads:[~2021-09-25 17:40 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-25 17:30 [PATCH v6 00/30] LoongArch64 port of QEMU TCG WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 01/30] elf: Add machine type value for LoongArch WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 03/30] tcg/loongarch64: Add the tcg-target.h file WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets WANG Xuerui
2021-09-25 17:30 ` WANG Xuerui [this message]
2021-09-25 17:30 ` [PATCH v6 07/30] tcg/loongarch64: Implement necessary relocation operations WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 08/30] tcg/loongarch64: Implement the memory barrier op WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi WANG Xuerui
2021-09-26  6:48   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 10/30] tcg/loongarch64: Implement goto_ptr WANG Xuerui
2021-09-29 17:13   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 11/30] tcg/loongarch64: Implement sign-/zero-extension ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 13/30] tcg/loongarch64: Implement deposit/extract ops WANG Xuerui
2021-09-29 17:14   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops WANG Xuerui
2021-09-26  6:50   ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 15/30] tcg/loongarch64: Implement clz/ctz ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 17/30] tcg/loongarch64: Implement add/sub ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 19/30] tcg/loongarch64: Implement br/brcond ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 20/30] tcg/loongarch64: Implement setcond ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 21/30] tcg/loongarch64: Implement tcg_out_call WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 22/30] tcg/loongarch64: Implement simple load/store ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 25/30] tcg/loongarch64: Implement exit_tb/goto_tb WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 26/30] tcg/loongarch64: Implement tcg_target_init WANG Xuerui
2021-09-26  7:15   ` Philippe Mathieu-Daudé
2021-09-26 23:07     ` Richard Henderson
2021-09-29 17:00       ` WANG Xuerui
2021-09-29 17:11       ` Philippe Mathieu-Daudé
2021-09-25 17:30 ` [PATCH v6 27/30] tcg/loongarch64: Register the JIT WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 28/30] linux-user: Add safe syscall handling for loongarch64 hosts WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler " WANG Xuerui
2021-09-25 17:30 ` [PATCH v6 30/30] configure, meson.build: Mark support " WANG Xuerui
2021-09-26  7:17   ` Philippe Mathieu-Daudé

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