From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org, laurent@vivier.eu
Subject: [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv
Date: Fri, 1 Oct 2021 13:11:41 -0400 [thread overview]
Message-ID: <20211001171151.1739472-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211001171151.1739472-1-richard.henderson@linaro.org>
Because the linux-user kuser page handling is currently implemented
by detecting magic addresses in the unnamed 0xaa trap, we cannot
simply remove nios2_cpu_tlb_fill and rely on the fallback code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 6 ++++++
target/nios2/cpu.c | 6 ++++--
target/nios2/helper.c | 7 ++++---
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index a80587338a..1a69ed7a49 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
MMU_SUPERVISOR_IDX;
}
+#ifdef CONFIG_USER_ONLY
+void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#endif
static inline int cpu_interrupts_enabled(CPUNios2State *env)
{
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1..421cad114a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
- .tlb_fill = nios2_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = nios2_cpu_record_sigsegv,
+#else
+ .tlb_fill = nios2_cpu_tlb_fill,
.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.do_interrupt = nios2_cpu_do_interrupt,
.do_unaligned_access = nios2_cpu_do_unaligned_access,
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 53be8398e9..e5c98650e1 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[R_EA] = env->regs[R_PC] + 4;
}
-bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
+ /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */
cs->exception_index = 0xaa;
cpu_loop_exit_restore(cs, retaddr);
}
--
2.25.1
next prev parent reply other threads:[~2021-10-01 17:56 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 17:11 [PATCH v3 00/41] linux-user: Streamline handling of SIGSEGV Richard Henderson
2021-10-01 17:11 ` [PATCH v3 01/41] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-10-01 17:11 ` [PATCH v3 02/41] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
2021-10-01 17:11 ` [PATCH v3 03/41] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
2021-10-01 17:11 ` [PATCH v3 04/41] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
2021-10-01 17:11 ` [PATCH v3 05/41] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
2021-10-01 17:11 ` [PATCH v3 06/41] linux-user: Reorg handling for SIGSEGV Richard Henderson
2021-10-01 17:11 ` [PATCH v3 07/41] linux-user/host/x86: Populate host_signal.h Richard Henderson
2021-10-01 17:11 ` [PATCH v3 08/41] linux-user/host/ppc: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 09/41] linux-user/host/alpha: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 10/41] linux-user/host/sparc: " Richard Henderson
2021-10-02 14:14 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 11/41] linux-user/host/arm: " Richard Henderson
2021-10-02 14:15 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 12/41] linux-user/host/aarch64: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 13/41] linux-user/host/s390: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 14/41] linux-user/host/mips: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 15/41] linux-user/host/riscv: " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 16/41] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-10-01 17:11 ` [PATCH v3 17/41] linux-user/host/riscv: Improve host_signal_write Richard Henderson
2021-10-01 17:11 ` [PATCH v3 18/41] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
2021-10-01 17:11 ` [PATCH v3 19/41] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 20/41] linux-user: Add cpu_loop_exit_segv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 21/41] target/alpha: Make alpha_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:18 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 22/41] target/arm: Use cpu_loop_exit_segv for mte tag lookup Richard Henderson
2021-10-02 14:20 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 23/41] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 24/41] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` [PATCH v3 25/41] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
2021-10-01 22:38 ` Taylor Simpson
2021-10-01 17:11 ` [PATCH v3 26/41] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` [PATCH v3 27/41] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 28/41] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:21 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 29/41] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
2021-10-01 17:11 ` [PATCH v3 30/41] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
2021-10-02 14:23 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` Richard Henderson [this message]
2021-10-02 14:24 ` [PATCH v3 31/41] target/nios2: Implement nios2_cpu_record_sigsegv Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 32/41] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Richard Henderson
2021-10-01 17:11 ` [PATCH v3 33/41] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:26 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 34/41] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 35/41] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
2021-10-02 14:27 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 36/41] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
2021-10-01 17:11 ` [PATCH v3 37/41] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
2021-10-01 17:11 ` [PATCH v3 38/41] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
2021-10-01 17:11 ` [PATCH v3 39/41] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
2021-10-02 14:28 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 40/41] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
2021-10-01 20:58 ` Max Filippov
2021-10-02 14:29 ` Philippe Mathieu-Daudé
2021-10-01 17:11 ` [PATCH v3 41/41] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
2021-10-02 14:30 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211001171151.1739472-32-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alex.bennee@linaro.org \
--cc=laurent@vivier.eu \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).