From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>
Subject: [PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
Date: Sun, 3 Oct 2021 19:57:37 +0200 [thread overview]
Message-ID: <20211003175743.3738710-3-f4bug@amsat.org> (raw)
In-Reply-To: <20211003175743.3738710-1-f4bug@amsat.org>
Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ee6424126f7..20036ae4968 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1650,7 +1650,7 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
- TCGv_i32 tdf = tcg_const_i32(df);
+ TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_SLDI_df:
@@ -1748,7 +1748,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(tn);
- tcg_temp_free_i32(tdf);
}
static void gen_msa_elm(DisasContext *ctx)
--
2.31.1
next prev parent reply other threads:[~2021-10-03 18:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-03 17:57 [PATCH 0/8] target/mips: Use tcg_constant_* Philippe Mathieu-Daudé
2021-10-03 17:57 ` [PATCH 1/8] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-03 17:57 ` Philippe Mathieu-Daudé [this message]
2021-10-03 19:25 ` [PATCH 2/8] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() Richard Henderson
2021-10-03 17:57 ` [PATCH 3/8] target/mips: Use tcg_constant_i32() in gen_msa_2rf() Philippe Mathieu-Daudé
2021-10-03 19:26 ` Richard Henderson
2021-10-03 17:57 ` [PATCH 4/8] target/mips: Use tcg_constant_i32() in gen_msa_2r() Philippe Mathieu-Daudé
2021-10-03 19:28 ` Richard Henderson
2021-10-03 17:57 ` [PATCH 5/8] target/mips: Use tcg_constant_i32() in gen_msa_3rf() Philippe Mathieu-Daudé
2021-10-03 19:30 ` Richard Henderson
2021-10-03 17:57 ` [PATCH 6/8] target/mips: Use explicit extract32() calls in gen_msa_i5() Philippe Mathieu-Daudé
2021-10-03 19:35 ` Richard Henderson
2021-10-03 17:57 ` [PATCH 7/8] target/mips: Use tcg_constant_i32() " Philippe Mathieu-Daudé
2021-10-03 19:37 ` Richard Henderson
2021-10-03 17:57 ` [PATCH 8/8] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() Philippe Mathieu-Daudé
2021-10-03 19:37 ` Richard Henderson
2021-10-11 22:22 ` [PATCH 0/8] target/mips: Use tcg_constant_* Philippe Mathieu-Daudé
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