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Wed, 6 Oct 2021 23:50:14 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.32]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4HQ24y34Kjz1RvTg; Wed, 6 Oct 2021 23:50:09 -0700 (PDT) From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: alistair23@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Alistair Francis Subject: [PULL 23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Date: Thu, 7 Oct 2021 16:47:48 +1000 Message-Id: <20211007064751.608580-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> References: <20211007064751.608580-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=907902f29=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daud=C3=A9 - Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 20210925133407.1259392-4-f4bug@amsat.org Signed-off-by: Alistair Francis --- include/hw/char/mchp_pfsoc_mmuart.h | 12 +++- hw/char/mchp_pfsoc_mmuart.c | 97 +++++++++++++++++++++++++---- 2 files changed, 93 insertions(+), 16 deletions(-) diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_p= fsoc_mmuart.h index 864ac1a36b..b0e14ca355 100644 --- a/include/hw/char/mchp_pfsoc_mmuart.h +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -28,17 +28,23 @@ #ifndef HW_MCHP_PFSOC_MMUART_H #define HW_MCHP_PFSOC_MMUART_H =20 +#include "hw/sysbus.h" #include "hw/char/serial.h" =20 #define MCHP_PFSOC_MMUART_REG_COUNT 13 =20 +#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart" +OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART) + typedef struct MchpPfSoCMMUartState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ MemoryRegion container; MemoryRegion iomem; - hwaddr base; - qemu_irq irq; =20 - SerialMM *serial; + SerialMM serial_mm; =20 uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT]; } MchpPfSoCMMUartState; diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index ea58655976..22f3e78eb9 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -22,8 +22,10 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "chardev/char.h" +#include "qapi/error.h" +#include "migration/vmstate.h" #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/qdev-properties.h" =20 #define REGS_OFFSET 0x20 =20 @@ -67,26 +69,95 @@ static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D= { }, }; =20 -MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, - hwaddr base, qemu_irq irq, Chardev *chr) +static void mchp_pfsoc_mmuart_reset(DeviceState *dev) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); + + memset(s->reg, 0, sizeof(s->reg)); + device_cold_reset(DEVICE(&s->serial_mm)); +} + +static void mchp_pfsoc_mmuart_init(Object *obj) { - MchpPfSoCMMUartState *s; + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(obj); =20 - s =3D g_new0(MchpPfSoCMMUartState, 1); + object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL= _MM); + object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "ch= ardev"); +} =20 - memory_region_init(&s->container, NULL, "mchp.pfsoc.mmuart", 0x1000)= ; +static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp) +{ + MchpPfSoCMMUartState *s =3D MCHP_PFSOC_UART(dev); =20 - memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2); + qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193); + qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness", + DEVICE_LITTLE_ENDIAN); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) { + return; + } + + sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm)); + + memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x= 1000); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); + + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm)= , 0)); + + memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, = s, "mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET= ); memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem); +} =20 - s->base =3D base; - s->irq =3D irq; +static const VMStateDescription mchp_pfsoc_mmuart_vmstate =3D { + .name =3D "mchp.pfsoc.uart", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState, + MCHP_PFSOC_MMUART_REG_COUNT), + VMSTATE_END_OF_LIST() + } +}; + +static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D mchp_pfsoc_mmuart_realize; + dc->reset =3D mchp_pfsoc_mmuart_reset; + dc->vmsd =3D &mchp_pfsoc_mmuart_vmstate; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); +} + +static const TypeInfo mchp_pfsoc_mmuart_info =3D { + .name =3D TYPE_MCHP_PFSOC_UART, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MchpPfSoCMMUartState), + .instance_init =3D mchp_pfsoc_mmuart_init, + .class_init =3D mchp_pfsoc_mmuart_class_init, +}; + +static void mchp_pfsoc_mmuart_register_types(void) +{ + type_register_static(&mchp_pfsoc_mmuart_info); +} + +type_init(mchp_pfsoc_mmuart_register_types) + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, + qemu_irq irq, Chardev *ch= r) +{ + DeviceState *dev =3D qdev_new(TYPE_MCHP_PFSOC_UART); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 - s->serial =3D serial_mm_init(&s->container, 0, 2, irq, 399193, chr, - DEVICE_LITTLE_ENDIAN); + qdev_prop_set_chr(dev, "chardev", chr); + sysbus_realize(sbd, &error_fatal); =20 - memory_region_add_subregion(sysmem, base, &s->container); + memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd= , 0)); + sysbus_connect_irq(sbd, 0, irq); =20 - return s; + return MCHP_PFSOC_UART(dev); } --=20 2.31.1