From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)
Date: Thu, 7 Oct 2021 16:47:32 +1000 [thread overview]
Message-ID: <20211007064751.608580-8-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20211007064751.608580-1-alistair.francis@opensource.wdc.com>
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
The Zb[abcs] ratification package does not include the proposed
shift-one instructions. There currently is no clear plan to whether
these (or variants of them) will be ratified as Zbo (or a different
extension) or what the timeframe for such a decision could be.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-8-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 8 ---
target/riscv/insn_trans/trans_rvb.c.inc | 70 -------------------------
2 files changed, 78 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b499691a9e..e0f6e315a2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -693,8 +693,6 @@ bset 0010100 .......... 001 ..... 0110011 @r
bclr 0100100 .......... 001 ..... 0110011 @r
binv 0110100 .......... 001 ..... 0110011 @r
bext 0100100 .......... 101 ..... 0110011 @r
-slo 0010000 .......... 001 ..... 0110011 @r
-sro 0010000 .......... 101 ..... 0110011 @r
ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
@@ -704,8 +702,6 @@ bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
binvi 01101. ........... 001 ..... 0010011 @sh
bexti 01001. ........... 101 ..... 0010011 @sh
-sloi 00100. ........... 001 ..... 0010011 @sh
-sroi 00100. ........... 101 ..... 0010011 @sh
rori 01100. ........... 101 ..... 0010011 @sh
grevi 01101. ........... 101 ..... 0010011 @sh
gorci 00101. ........... 101 ..... 0010011 @sh
@@ -717,15 +713,11 @@ cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
-slow 0010000 .......... 001 ..... 0111011 @r
-srow 0010000 .......... 101 ..... 0111011 @r
rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
-sloiw 0010000 .......... 001 ..... 0011011 @sh5
-sroiw 0010000 .......... 101 ..... 0011011 @sh5
roriw 0110000 .......... 101 ..... 0011011 @sh5
greviw 0110100 .......... 101 ..... 0011011 @sh5
gorciw 0010100 .......... 101 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index fbe1c3b410..a5bf40f95b 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -237,44 +237,6 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
}
-static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shl_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_slo(DisasContext *ctx, arg_slo *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
-{
- tcg_gen_not_tl(ret, arg1);
- tcg_gen_shr_tl(ret, ret, arg2);
- tcg_gen_not_tl(ret, ret);
-}
-
-static bool trans_sro(DisasContext *ctx, arg_sro *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
-{
- REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_EXT(ctx, RVB);
@@ -420,38 +382,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, EXT_NONE, gen_packuw);
}
-static bool trans_slow(DisasContext *ctx, arg_slow *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_slo);
-}
-
-static bool trans_srow(DisasContext *ctx, arg_srow *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
-}
-
-static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
-{
- REQUIRE_64BIT(ctx);
- REQUIRE_EXT(ctx, RVB);
- ctx->w = true;
- return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_sro);
-}
-
static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
{
TCGv_i32 t1 = tcg_temp_new_i32();
--
2.31.1
next prev parent reply other threads:[~2021-10-07 6:52 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 6:47 [PULL 00/26] riscv-to-apply queue Alistair Francis
2021-10-07 6:47 ` [PULL 01/26] target/riscv: Introduce temporary in gen_add_uw() Alistair Francis
2021-10-07 6:47 ` [PULL 02/26] target/riscv: fix clzw implementation to operate on arg1 Alistair Francis
2021-10-07 6:47 ` [PULL 03/26] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Alistair Francis
2021-10-07 6:47 ` [PULL 04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Alistair Francis
2021-10-07 6:47 ` [PULL 05/26] target/riscv: Reassign instructions to the Zba-extension Alistair Francis
2021-10-07 6:47 ` [PULL 06/26] target/riscv: Remove the W-form instructions from Zbs Alistair Francis
2021-10-07 6:47 ` Alistair Francis [this message]
2021-10-07 6:47 ` [PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension Alistair Francis
2021-10-07 6:47 ` [PULL 09/26] target/riscv: Add instructions of the Zbc-extension Alistair Francis
2021-10-07 6:47 ` [PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension Alistair Francis
2021-10-07 6:47 ` [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Alistair Francis
2021-10-13 9:36 ` Vincent Palatin
2021-10-13 9:37 ` [PATCH v1A] target/riscv: fix orc.b instruction in the Zbb extension Vincent Palatin
2021-10-13 9:38 ` [PATCH v1B] " Vincent Palatin
2021-10-13 13:12 ` [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-10-13 13:44 ` Vincent Palatin
2021-10-13 13:49 ` Philipp Tomsich
2021-10-13 16:20 ` Vineet Gupta
2021-10-13 16:51 ` Richard Henderson
2021-10-13 17:00 ` Philipp Tomsich
2021-10-07 6:47 ` [PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro Alistair Francis
2021-10-07 6:47 ` [PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi Alistair Francis
2021-10-07 6:47 ` [PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Alistair Francis
2021-10-07 6:47 ` [PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs]) Alistair Francis
2021-10-07 6:47 ` [PULL 16/26] disas/riscv: Add Zb[abcs] instructions Alistair Francis
2021-10-07 6:47 ` [PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() Alistair Francis
2021-10-07 6:47 ` [PULL 18/26] hw/char: ibex_uart: Register device in 'input' category Alistair Francis
2021-10-07 6:47 ` [PULL 19/26] hw/char: shakti_uart: " Alistair Francis
2021-10-07 6:47 ` [PULL 20/26] hw/char: sifive_uart: " Alistair Francis
2021-10-07 6:47 ` [PULL 21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition Alistair Francis
2021-10-07 6:47 ` [PULL 22/26] hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container Alistair Francis
2021-10-07 6:47 ` [PULL 23/26] hw/char/mchp_pfsoc_mmuart: QOM'ify PolarFire MMUART Alistair Francis
2021-10-07 6:47 ` [PULL 24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection Alistair Francis
2021-10-07 6:47 ` [PULL 25/26] hw/dma: sifive_pdma: Don't run DMA when channel is disclaimed Alistair Francis
2021-10-07 6:47 ` [PULL 26/26] hw/riscv: shakti_c: Mark as not user creatable Alistair Francis
2021-10-07 17:25 ` [PULL 00/26] riscv-to-apply queue Richard Henderson
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