From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org
Subject: [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64
Date: Thu, 7 Oct 2021 10:47:15 -0700 [thread overview]
Message-ID: <20211007174722.929993-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org>
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1..bbc5c93ef1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
static bool amo_check64(DisasContext *s, arg_rwdvm* a)
{
- return !is_32bit(s) && amo_check(s, a);
+ REQUIRE_64BIT(s);
+ return amo_check(s, a);
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
--
2.25.1
next prev parent reply other threads:[~2021-10-07 18:02 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-07 17:47 [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-07 17:47 ` [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-08 2:28 ` Alistair Francis
2021-10-13 12:13 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-11 23:28 ` Alistair Francis
2021-10-13 12:18 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-07 17:47 ` [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-13 16:46 ` Frédéric Pétrot
2021-10-13 16:54 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-07 17:47 ` Richard Henderson [this message]
2021-10-07 17:47 ` [PATCH 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-07 17:47 ` [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-07 17:47 ` [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-07 17:47 ` [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 11:54 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-13 11:45 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 8:31 ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-13 11:24 ` LIU Zhiwei
2021-10-10 15:17 ` [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Frédéric Pétrot
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