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[68.185.26.38]) by smtp.gmail.com with ESMTPSA id 18sm5095391pfh.115.2021.10.10.10.44.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Oct 2021 10:44:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 0/8] tcg: support 32-bit guest addresses as signed Date: Sun, 10 Oct 2021 10:43:53 -0700 Message-Id: <20211010174401.141339-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We have 2, and nearly 3, hosts that naturally produce sign-extended values, and have to work extra hard (with 1 or 2 insns) to produce the zero-extended address that we expect today. However, it's a simple matter of arithmetic for the middle-end to require sign-extended addresses instead. For user-only, we do have to be careful not to allow a guest object to wrap around the signed boundary, but that's fairly easily done. Tested with aarch64, as that's the best hw currently available. r~ Richard Henderson (8): tcg: Add TCG_TARGET_SIGNED_ADDR32 accel/tcg: Split out g2h_tlbe accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu accel/tcg: Add guest_base_signed_addr32 for user-only linux-user: Support TCG_TARGET_SIGNED_ADDR32 tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32 target/mips: Support TCG_TARGET_SIGNED_ADDR32 target/riscv: Support TCG_TARGET_SIGNED_ADDR32 include/exec/cpu-all.h | 20 ++++++++--- include/exec/cpu_ldst.h | 3 +- tcg/aarch64/tcg-target-sa32.h | 7 ++++ tcg/arm/tcg-target-sa32.h | 1 + tcg/i386/tcg-target-sa32.h | 1 + tcg/mips/tcg-target-sa32.h | 9 +++++ tcg/ppc/tcg-target-sa32.h | 1 + tcg/riscv/tcg-target-sa32.h | 5 +++ tcg/s390x/tcg-target-sa32.h | 1 + tcg/sparc/tcg-target-sa32.h | 1 + tcg/tci/tcg-target-sa32.h | 1 + accel/tcg/cputlb.c | 36 +++++++++++++------ bsd-user/main.c | 4 +++ linux-user/elfload.c | 62 +++++++++++++++++++++++++------- linux-user/main.c | 3 ++ tcg/aarch64/tcg-target.c.inc | 68 ++++++++++++++++++++++------------- tcg/mips/tcg-target.c.inc | 13 ++----- tcg/riscv/tcg-target.c.inc | 8 ++--- 18 files changed, 176 insertions(+), 68 deletions(-) create mode 100644 tcg/aarch64/tcg-target-sa32.h create mode 100644 tcg/arm/tcg-target-sa32.h create mode 100644 tcg/i386/tcg-target-sa32.h create mode 100644 tcg/mips/tcg-target-sa32.h create mode 100644 tcg/ppc/tcg-target-sa32.h create mode 100644 tcg/riscv/tcg-target-sa32.h create mode 100644 tcg/s390x/tcg-target-sa32.h create mode 100644 tcg/sparc/tcg-target-sa32.h create mode 100644 tcg/tci/tcg-target-sa32.h -- 2.25.1