From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: git@xen0n.name, Alistair.Francis@wdc.com, f4bug@amsat.org
Subject: [PATCH 7/8] target/mips: Support TCG_TARGET_SIGNED_ADDR32
Date: Sun, 10 Oct 2021 10:44:00 -0700 [thread overview]
Message-ID: <20211010174401.141339-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211010174401.141339-1-richard.henderson@linaro.org>
All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-sa32.h | 8 ++++++++
tcg/mips/tcg-target.c.inc | 13 +++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
index cb185b1526..51255e7cba 100644
--- a/tcg/mips/tcg-target-sa32.h
+++ b/tcg/mips/tcg-target-sa32.h
@@ -1 +1,9 @@
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#ifdef __mips64
+#define TCG_TARGET_SIGNED_ADDR32 1
+#else
#define TCG_TARGET_SIGNED_ADDR32 0
+#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index d8f6914f03..cc3b4d5b90 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1161,20 +1161,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF);
tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
} else {
- tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD
- : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW),
- TCG_TMP0, TCG_TMP3, cmp_off);
+ tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off);
tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
/* No second compare is required here;
load the tlb addend for the fast path. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off);
}
- /* Zero extend a 32-bit guest address for a 64-bit host. */
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addrl);
- addrl = base;
- }
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
label_ptr[0] = s->code_ptr;
@@ -1456,7 +1449,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
@@ -1559,7 +1552,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
s->code_ptr, label_ptr);
#else
base = TCG_REG_A0;
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
--
2.25.1
next prev parent reply other threads:[~2021-10-10 17:49 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 17:43 [PATCH 0/8] tcg: support 32-bit guest addresses as signed Richard Henderson
2021-10-10 17:43 ` [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 4:21 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 22:07 ` Philippe Mathieu-Daudé
2021-10-11 23:16 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 2/8] accel/tcg: Split out g2h_tlbe Richard Henderson
2021-10-11 4:22 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 21:48 ` Philippe Mathieu-Daudé
2021-10-11 23:19 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
2021-10-11 4:30 ` WANG Xuerui
2021-10-11 15:27 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 4/8] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
2021-10-11 22:06 ` Philippe Mathieu-Daudé
2021-10-13 7:07 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 10:22 ` Alex Bennée
2021-10-11 15:32 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 6/8] tcg/aarch64: " Richard Henderson
2021-10-11 10:28 ` Alex Bennée
2021-10-11 15:24 ` Richard Henderson
2021-10-13 21:05 ` Richard Henderson
2021-10-10 17:44 ` Richard Henderson [this message]
2021-10-11 4:20 ` [PATCH 7/8] target/mips: " WANG Xuerui
2021-10-13 22:24 ` Richard Henderson
2021-10-10 17:44 ` [PATCH 8/8] target/riscv: " Richard Henderson
2021-10-11 22:00 ` Philippe Mathieu-Daudé
2021-10-13 7:08 ` Alistair Francis
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