From: Simon Glass <sjg@chromium.org>
To: U-Boot Mailing List <u-boot@lists.denx.de>
Cc: Tom Rini <trini@konsulko.com>,
qemu-devel@nongnu.org, Leo <ycliang@andestech.com>,
David Abdurachmanov <david.abdurachmanov@sifive.com>,
Simon Glass <sjg@chromium.org>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>,
Rick Chen <rick@andestech.com>, Green Wan <green.wan@sifive.com>,
Sean Anderson <seanga2@gmail.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Zong Li <zong.li@sifive.com>,
Tianrui Wei <tianrui-wei@outlook.com>,
Bin Meng <bmeng.cn@gmail.com>,
Dimitri John Ledkov <dimitri.ledkov@canonical.com>,
Padmarao Begari <padmarao.begari@microchip.com>
Subject: [PATCH 06/16] riscv: qemu: Add devicetree files for qemu_riscv32/64
Date: Tue, 12 Oct 2021 19:01:10 -0600 [thread overview]
Message-ID: <20211013010120.96851-7-sjg@chromium.org> (raw)
In-Reply-To: <20211013010120.96851-1-sjg@chromium.org>
Add these files, generated from qemu, so there is a reference devicetree
in the U-Boot tree.
Split the existing qemu-virt into two, since we need a different
devicetree for 32- and 64-bit machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/qemu-virt.dts | 8 -
arch/riscv/dts/qemu-virt32.dts | 217 +++++++++++++++++++++++++++
arch/riscv/dts/qemu-virt64.dts | 217 +++++++++++++++++++++++++++
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv32_smode_defconfig | 1 +
configs/qemu-riscv32_spl_defconfig | 2 +-
configs/qemu-riscv64_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
configs/qemu-riscv64_spl_defconfig | 2 +-
10 files changed, 441 insertions(+), 11 deletions(-)
delete mode 100644 arch/riscv/dts/qemu-virt.dts
create mode 100644 arch/riscv/dts/qemu-virt32.dts
create mode 100644 arch/riscv/dts/qemu-virt64.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b6e9166767b..90d3f35e6e3 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -2,7 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
-dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts
deleted file mode 100644
index fecff542b91..00000000000
--- a/arch/riscv/dts/qemu-virt.dts
+++ /dev/null
@@ -1,8 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
- */
-
-/dts-v1/;
-
-#include "binman.dtsi"
diff --git a/arch/riscv/dts/qemu-virt32.dts b/arch/riscv/dts/qemu-virt32.dts
new file mode 100644
index 00000000000..3c449413523
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt32.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "riscv-virtio";
+ model = "riscv-virtio,qemu";
+
+ fw-cfg@10100000 {
+ dma-coherent;
+ reg = <0x00 0x10100000 0x00 0x18>;
+ compatible = "qemu,fw-cfg-mmio";
+ };
+
+ flash@20000000 {
+ bank-width = <0x04>;
+ reg = <0x00 0x20000000 0x00 0x2000000
+ 0x00 0x22000000 0x00 0x2000000>;
+ compatible = "cfi-flash";
+ };
+
+ chosen {
+ bootargs = [00];
+ stdout-path = "/soc/uart@10000000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x8000000>;
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0x989680>;
+
+ cpu@0 {
+ phandle = <0x01>;
+ device_type = "cpu";
+ reg = <0x00>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv32imafdcsu";
+ mmu-type = "riscv,sv32";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x02>;
+ };
+ };
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x01>;
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "simple-bus";
+ ranges;
+
+ rtc@101000 {
+ interrupts = <0x0b>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x101000 0x00 0x1000>;
+ compatible = "google,goldfish-rtc";
+ };
+
+ uart@10000000 {
+ interrupts = <0x0a>;
+ interrupt-parent = <0x03>;
+ clock-frequency = <0x384000>;
+ reg = <0x00 0x10000000 0x00 0x100>;
+ compatible = "ns16550a";
+ };
+
+ poweroff {
+ value = <0x5555>;
+ offset = <0x00>;
+ regmap = <0x04>;
+ compatible = "syscon-poweroff";
+ };
+
+ reboot {
+ value = <0x7777>;
+ offset = <0x00>;
+ regmap = <0x04>;
+ compatible = "syscon-reboot";
+ };
+
+ test@100000 {
+ phandle = <0x04>;
+ reg = <0x00 0x100000 0x00 0x1000>;
+ compatible = "sifive,test1\0sifive,test0\0syscon";
+ };
+
+ pci@30000000 {
+ interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00
+ 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03
+ 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23
+ 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00
+ 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03
+ 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20
+ 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00
+ 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03
+ 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21
+ 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00
+ 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03
+ 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
+ ranges = <0x1000000 0x00 0x00 0x00
+ 0x3000000 0x00 0x10000 0x2000000
+ 0x00 0x40000000 0x00 0x40000000
+ 0x00 0x40000000 0x3000000 0x03
+ 0x00 0x03 0x00 0x01
+ 0x00>;
+ reg = <0x00 0x30000000 0x00 0x10000000>;
+ dma-coherent;
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x03>;
+ };
+
+ virtio_mmio@10008000 {
+ interrupts = <0x08>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10008000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x06>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10006000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10005000 {
+ interrupts = <0x05>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10005000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10004000 {
+ interrupts = <0x04>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10004000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10003000 {
+ interrupts = <0x03>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10002000 {
+ interrupts = <0x02>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10002000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10001000 {
+ interrupts = <0x01>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10001000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ plic@c000000 {
+ phandle = <0x03>;
+ riscv,ndev = <0x35>;
+ reg = <0x00 0xc000000 0x00 0x210000>;
+ interrupts-extended = <0x02 0x0b 0x02 0x09>;
+ interrupt-controller;
+ compatible = "sifive,plic-1.0.0\0riscv,plic0";
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x00>;
+ };
+
+ clint@2000000 {
+ interrupts-extended = <0x02 0x03 0x02 0x07>;
+ reg = <0x00 0x2000000 0x00 0x10000>;
+ compatible = "sifive,clint0\0riscv,clint0";
+ };
+ };
+};
diff --git a/arch/riscv/dts/qemu-virt64.dts b/arch/riscv/dts/qemu-virt64.dts
new file mode 100644
index 00000000000..61bc084e280
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt64.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "riscv-virtio";
+ model = "riscv-virtio,qemu";
+
+ fw-cfg@10100000 {
+ dma-coherent;
+ reg = <0x00 0x10100000 0x00 0x18>;
+ compatible = "qemu,fw-cfg-mmio";
+ };
+
+ flash@20000000 {
+ bank-width = <0x04>;
+ reg = <0x00 0x20000000 0x00 0x2000000
+ 0x00 0x22000000 0x00 0x2000000>;
+ compatible = "cfi-flash";
+ };
+
+ chosen {
+ bootargs = [00];
+ stdout-path = "/soc/uart@10000000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x00 0x80000000 0x00 0x8000000>;
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ timebase-frequency = <0x989680>;
+
+ cpu@0 {
+ phandle = <0x01>;
+ device_type = "cpu";
+ reg = <0x00>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdcsu";
+ mmu-type = "riscv,sv48";
+
+ interrupt-controller {
+ #interrupt-cells = <0x01>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ phandle = <0x02>;
+ };
+ };
+
+ cpu-map {
+
+ cluster0 {
+
+ core0 {
+ cpu = <0x01>;
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ compatible = "simple-bus";
+ ranges;
+
+ rtc@101000 {
+ interrupts = <0x0b>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x101000 0x00 0x1000>;
+ compatible = "google,goldfish-rtc";
+ };
+
+ uart@10000000 {
+ interrupts = <0x0a>;
+ interrupt-parent = <0x03>;
+ clock-frequency = <0x384000>;
+ reg = <0x00 0x10000000 0x00 0x100>;
+ compatible = "ns16550a";
+ };
+
+ poweroff {
+ value = <0x5555>;
+ offset = <0x00>;
+ regmap = <0x04>;
+ compatible = "syscon-poweroff";
+ };
+
+ reboot {
+ value = <0x7777>;
+ offset = <0x00>;
+ regmap = <0x04>;
+ compatible = "syscon-reboot";
+ };
+
+ test@100000 {
+ phandle = <0x04>;
+ reg = <0x00 0x100000 0x00 0x1000>;
+ compatible = "sifive,test1\0sifive,test0\0syscon";
+ };
+
+ pci@30000000 {
+ interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
+ interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00
+ 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03
+ 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23
+ 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00
+ 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03
+ 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20
+ 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00
+ 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03
+ 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21
+ 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00
+ 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03
+ 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
+ ranges = <0x1000000 0x00 0x00 0x00
+ 0x3000000 0x00 0x10000 0x2000000
+ 0x00 0x40000000 0x00 0x40000000
+ 0x00 0x40000000 0x3000000 0x03
+ 0x00 0x03 0x00 0x01
+ 0x00>;
+ reg = <0x00 0x30000000 0x00 0x10000000>;
+ dma-coherent;
+ bus-range = <0x00 0xff>;
+ linux,pci-domain = <0x00>;
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ #size-cells = <0x02>;
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x03>;
+ };
+
+ virtio_mmio@10008000 {
+ interrupts = <0x08>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10008000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10007000 {
+ interrupts = <0x07>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10007000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10006000 {
+ interrupts = <0x06>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10006000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10005000 {
+ interrupts = <0x05>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10005000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10004000 {
+ interrupts = <0x04>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10004000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10003000 {
+ interrupts = <0x03>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10003000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10002000 {
+ interrupts = <0x02>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10002000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ virtio_mmio@10001000 {
+ interrupts = <0x01>;
+ interrupt-parent = <0x03>;
+ reg = <0x00 0x10001000 0x00 0x1000>;
+ compatible = "virtio,mmio";
+ };
+
+ plic@c000000 {
+ phandle = <0x03>;
+ riscv,ndev = <0x35>;
+ reg = <0x00 0xc000000 0x00 0x210000>;
+ interrupts-extended = <0x02 0x0b 0x02 0x09>;
+ interrupt-controller;
+ compatible = "sifive,plic-1.0.0\0riscv,plic0";
+ #interrupt-cells = <0x01>;
+ #address-cells = <0x00>;
+ };
+
+ clint@2000000 {
+ interrupts-extended = <0x02 0x03 0x02 0x07>;
+ reg = <0x00 0x2000000 0x00 0x10000>;
+ compatible = "sifive,clint0\0riscv,clint0";
+ };
+ };
+};
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
index e77e3ed53a0..54953cd347b 100644
--- a/configs/qemu-riscv32_defconfig
+++ b/configs/qemu-riscv32_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x80200000
diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
index 03787416f10..21ee08a643e 100644
--- a/configs/qemu-riscv32_smode_defconfig
+++ b/configs/qemu-riscv32_smode_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index b0e655be416..3909c9a15ad 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -2,7 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
index 1f8dc2d2053..303ad2d5f39 100644
--- a/configs/qemu-riscv64_defconfig
+++ b/configs/qemu-riscv64_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
index bdcec1fdaba..62cdf91699f 100644
--- a/configs/qemu-riscv64_smode_defconfig
+++ b/configs/qemu-riscv64_smode_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 9745c1a586a..34d88da41b0 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -2,7 +2,7 @@ CONFIG_RISCV=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x800000
-CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
CONFIG_SPL=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
--
2.33.0.882.g93a45727a2-goog
next prev parent reply other threads:[~2021-10-13 1:03 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 1:01 [PATCH 00/16] fdt: Make OF_BOARD a boolean option Simon Glass
2021-10-13 1:01 ` [PATCH 01/16] arm: qemu: Mention -nographic in the docs Simon Glass
2021-10-13 1:01 ` [PATCH 02/16] arm: qemu: Explain how to extract the generate devicetree Simon Glass
2021-10-13 1:19 ` François Ozog
2021-10-13 16:58 ` Simon Glass
2021-10-13 17:36 ` Tom Rini
2021-10-13 1:01 ` [PATCH 03/16] riscv: " Simon Glass
2021-10-13 1:01 ` [PATCH 04/16] arm: qemu: Add a devicetree file for qemu_arm Simon Glass
2021-10-13 1:01 ` [PATCH 05/16] arm: qemu: Add a devicetree file for qemu_arm64 Simon Glass
2021-10-13 1:15 ` François Ozog
2021-10-27 14:44 ` Alex Bennée
2021-10-27 14:56 ` Tom Rini
2021-10-27 18:34 ` Simon Glass
2021-10-27 18:39 ` Tom Rini
2021-10-27 19:45 ` Alex Bennée
2021-10-13 1:01 ` Simon Glass [this message]
2021-10-13 4:21 ` [PATCH 06/16] riscv: qemu: Add devicetree files for qemu_riscv32/64 Heinrich Schuchardt
2021-10-13 1:29 ` [PATCH 00/16] fdt: Make OF_BOARD a boolean option Bin Meng
2021-10-13 1:34 ` Tom Rini
2021-10-13 8:02 ` François Ozog
2021-10-13 14:47 ` Simon Glass
2021-10-13 17:34 ` François Ozog
2021-10-13 18:06 ` Simon Glass
2021-10-14 14:56 ` Tom Rini
2021-10-14 15:17 ` Simon Glass
2021-10-14 15:28 ` Tom Rini
2021-10-14 17:58 ` François Ozog
2021-10-15 18:03 ` Simon Glass
2021-10-26 6:46 ` Ilias Apalodimas
2021-10-27 12:59 ` Tom Rini
2021-10-27 13:30 ` François Ozog
2021-10-27 13:38 ` Tom Rini
2021-10-27 13:47 ` Ilias Apalodimas
2021-10-27 14:26 ` Tom Rini
2021-10-27 13:48 ` François Ozog
2021-10-27 14:30 ` Tom Rini
2021-10-28 2:50 ` Simon Glass
2021-10-28 8:21 ` François Ozog
2021-10-28 14:30 ` Simon Glass
2021-10-28 14:50 ` François Ozog
2021-10-28 15:44 ` Simon Glass
2021-10-28 16:25 ` François Ozog
2021-11-02 14:59 ` Simon Glass
2021-11-01 11:04 ` Ilias Apalodimas
2021-11-02 10:06 ` Michael Walle
2021-11-02 12:34 ` François Ozog
2021-11-02 14:59 ` Simon Glass
2021-10-27 12:48 ` Tom Rini
2021-10-27 13:15 ` François Ozog
2021-10-27 13:23 ` Heinrich Schuchardt
2021-10-27 14:55 ` Tom Rini
2021-10-27 15:02 ` Heinrich Schuchardt
2021-10-27 18:04 ` Tom Rini
2021-10-27 14:54 ` Tom Rini
2021-10-27 15:10 ` Mark Kettenis
2021-10-27 15:24 ` Simon Glass
2021-10-27 18:06 ` Tom Rini
2021-10-27 18:11 ` François Ozog
2021-10-27 21:52 ` Mark Kettenis
2021-10-27 16:02 ` François Ozog
2021-10-27 19:06 ` Tom Rini
2021-10-27 22:00 ` François Ozog
2021-10-28 14:41 ` Tom Rini
2021-10-14 16:24 ` Andre Przywara
2021-10-14 17:48 ` François Ozog
2021-10-14 18:12 ` François Ozog
2021-10-14 21:00 ` Simon Glass
2021-10-13 12:39 ` Philippe Mathieu-Daudé
2021-10-13 13:06 ` François Ozog
2021-10-13 4:26 ` Heinrich Schuchardt
2021-10-13 13:06 ` François Ozog
2021-10-13 9:50 ` Andre Przywara
2021-10-13 13:05 ` François Ozog
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