From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v4 43/48] tcg/aarch64: Support raising sigbus for user-only
Date: Tue, 12 Oct 2021 19:46:02 -0700 [thread overview]
Message-ID: <20211013024607.731881-44-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211013024607.731881-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 2 -
tcg/aarch64/tcg-target.c.inc | 91 +++++++++++++++++++++++++++++-------
2 files changed, 74 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 7a93ac8023..876af589ce 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -151,9 +151,7 @@ typedef enum {
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
-#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
-#endif
#define TCG_TARGET_NEED_POOL_LABELS
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 5edca8d44d..1f205f90b2 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -10,6 +10,7 @@
* See the COPYING file in the top-level directory for details.
*/
+#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "qemu/bitops.h"
@@ -443,6 +444,7 @@ typedef enum {
I3404_ANDI = 0x12000000,
I3404_ORRI = 0x32000000,
I3404_EORI = 0x52000000,
+ I3404_ANDSI = 0x72000000,
/* Move wide immediate instructions. */
I3405_MOVN = 0x12800000,
@@ -1328,8 +1330,9 @@ static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target)
if (offset == sextract64(offset, 0, 26)) {
tcg_out_insn(s, 3206, B, offset);
} else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
- tcg_out_insn(s, 3207, BR, TCG_REG_TMP);
+ /* Choose X9 as a call-clobbered non-LR temporary. */
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X9, (intptr_t)target);
+ tcg_out_insn(s, 3207, BR, TCG_REG_X9);
}
}
@@ -1541,9 +1544,14 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
}
}
-#ifdef CONFIG_SOFTMMU
-#include "../tcg-ldst.c.inc"
+static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
+{
+ ptrdiff_t offset = tcg_pcrel_diff(s, target);
+ tcg_debug_assert(offset == sextract64(offset, 0, 21));
+ tcg_out_insn(s, 3406, ADR, rd, offset);
+}
+#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* MemOpIdx oi, uintptr_t ra)
*/
@@ -1577,13 +1585,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = {
#endif
};
-static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
-{
- ptrdiff_t offset = tcg_pcrel_diff(s, target);
- tcg_debug_assert(offset == sextract64(offset, 0, 21));
- tcg_out_insn(s, 3406, ADR, rd, offset);
-}
-
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
MemOpIdx oi = lb->oi;
@@ -1714,15 +1715,58 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
}
+#else
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg,
+ unsigned a_bits)
+{
+ unsigned a_mask = (1 << a_bits) - 1;
+ TCGLabelQemuLdst *label = new_ldst_label(s);
+
+ label->is_ld = is_ld;
+ label->addrlo_reg = addr_reg;
+
+ /* tst addr, #mask */
+ tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
+
+ label->label_ptr[0] = s->code_ptr;
+
+ /* b.ne slow_path */
+ tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);
+
+ label->raddr = tcg_splitwx_to_rx(s->code_ptr);
+}
+
+static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
+ return false;
+ }
+
+ tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_X1, l->addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
+
+ /* "Tail call" to the helper, with the return address back inline. */
+ tcg_out_adr(s, TCG_REG_LR, l->raddr);
+ tcg_out_goto_long(s, (const void *)(l->is_ld ? helper_unaligned_ld
+ : helper_unaligned_st));
+ return true;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
#endif /* CONFIG_SOFTMMU */
static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- /* Byte swapping is left to middle-end expansion. */
- tcg_debug_assert((memop & MO_BSWAP) == 0);
-
switch (memop & MO_SSIZE) {
case MO_UB:
tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
@@ -1756,9 +1800,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
TCGReg data_r, TCGReg addr_r,
TCGType otype, TCGReg off_r)
{
- /* Byte swapping is left to middle-end expansion. */
- tcg_debug_assert((memop & MO_BSWAP) == 0);
-
switch (memop & MO_SIZE) {
case MO_8:
tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
@@ -1782,6 +1823,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((memop & MO_BSWAP) == 0);
+
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
@@ -1792,6 +1837,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
+ unsigned a_bits = get_alignment_bits(memop);
+ if (a_bits) {
+ tcg_out_test_alignment(s, true, addr_reg, a_bits);
+ }
if (USE_GUEST_BASE) {
tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
TCG_REG_GUEST_BASE, otype, addr_reg);
@@ -1807,6 +1856,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+
+ /* Byte swapping is left to middle-end expansion. */
+ tcg_debug_assert((memop & MO_BSWAP) == 0);
+
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
@@ -1817,6 +1870,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
data_reg, addr_reg, s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
+ unsigned a_bits = get_alignment_bits(memop);
+ if (a_bits) {
+ tcg_out_test_alignment(s, false, addr_reg, a_bits);
+ }
if (USE_GUEST_BASE) {
tcg_out_qemu_st_direct(s, memop, data_reg,
TCG_REG_GUEST_BASE, otype, addr_reg);
--
2.25.1
next prev parent reply other threads:[~2021-10-13 3:14 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 2:45 [PATCH v4 00/48] Richard Henderson
2021-10-13 2:45 ` [PATCH v4 01/48] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 02/48] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 03/48] linux-user/alpha: Remove EXCP_UNALIGN handling Richard Henderson
2021-10-13 2:45 ` [PATCH v4 04/48] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 05/48] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
2021-10-13 2:45 ` [PATCH v4 06/48] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
2021-10-13 2:45 ` [PATCH v4 07/48] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
2021-10-13 2:45 ` [PATCH v4 08/48] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-10-13 2:45 ` [PATCH v4 09/48] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-10-13 2:54 ` Warner Losh
2021-10-13 2:45 ` [PATCH v4 10/48] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 11/48] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
2021-10-13 2:45 ` [PATCH v4 12/48] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
2021-10-13 2:45 ` [PATCH v4 13/48] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
2021-10-13 2:45 ` [PATCH v4 14/48] target/sparc: Split out build_sfsr Richard Henderson
2021-10-13 2:45 ` [PATCH v4 15/48] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
2021-10-13 2:45 ` [PATCH v4 16/48] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-10-13 2:45 ` [PATCH v4 17/48] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-10-13 2:45 ` [PATCH v4 18/48] target/i386: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 19/48] target/ppc: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 20/48] target/s390x: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 21/48] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-10-13 2:45 ` [PATCH v4 22/48] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-10-13 2:45 ` [PATCH v4 23/48] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-10-13 2:45 ` [PATCH v4 24/48] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-10-13 2:45 ` [PATCH v4 25/48] target/mips: Use 8-byte memory ops " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 26/48] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-10-13 2:45 ` [PATCH v4 27/48] target/sparc: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 28/48] target/arm: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 29/48] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-10-13 2:45 ` [PATCH v4 30/48] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 31/48] linux-user: Split out do_prctl and subroutines Richard Henderson
2021-10-13 2:45 ` [PATCH v4 32/48] linux-user: Disable more prctl subcodes Richard Henderson
2021-10-13 2:45 ` [PATCH v4 33/48] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Richard Henderson
2021-10-13 2:45 ` [PATCH v4 34/48] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
2021-10-13 2:45 ` [PATCH v4 35/48] target/alpha: Reorg fp memory operations Richard Henderson
2021-10-13 2:45 ` [PATCH v4 36/48] target/alpha: Reorg integer " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 37/48] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
2021-10-13 2:45 ` [PATCH v4 38/48] target/hppa: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 39/48] target/sh4: " Richard Henderson
2021-10-13 2:45 ` [PATCH v4 40/48] linux-user/signal: Handle BUS_ADRALN in host_signal_handler Richard Henderson
2021-10-13 2:46 ` [PATCH v4 41/48] tcg: Canonicalize alignment flags in MemOp Richard Henderson
2021-10-13 2:46 ` [PATCH v4 42/48] tcg/i386: Support raising sigbus for user-only Richard Henderson
2021-10-13 2:46 ` Richard Henderson [this message]
2021-10-13 2:46 ` [PATCH v4 44/48] tcg/ppc: " Richard Henderson
2021-10-13 2:46 ` [PATCH v4 45/48] tcg/s390: " Richard Henderson
2021-10-13 2:46 ` [PATCH v4 46/48] tcg/tci: " Richard Henderson
2021-10-13 2:46 ` [PATCH v4 47/48] tcg/riscv: " Richard Henderson
2021-10-13 2:46 ` [PATCH v4 48/48] tests/tcg/multiarch: Add sigbus.c Richard Henderson
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