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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Taylor Simpson" <tsimpson@quicinc.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 06/15] target/hexagon: Implement cpu_mmu_index
Date: Wed, 13 Oct 2021 11:22:30 -0700	[thread overview]
Message-ID: <20211013182239.991127-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211013182239.991127-1-richard.henderson@linaro.org>

The function is trivial for user-only, but still must be present.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hexagon/cpu.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index f7d043865b..f90c187888 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -141,6 +141,15 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,
 #endif
 }
 
+static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+    return MMU_USER_IDX;
+#else
+#error System mode not supported on Hexagon yet
+#endif
+}
+
 typedef struct CPUHexagonState CPUArchState;
 typedef HexagonCPU ArchCPU;
 
-- 
2.25.1



  parent reply	other threads:[~2021-10-13 18:28 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-13 18:22 [PULL 00/15] tcg patch queue Richard Henderson
2021-10-13 18:22 ` [PULL 01/15] memory: Log access direction for invalid accesses Richard Henderson
2021-10-13 18:22 ` [PULL 02/15] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
2021-10-13 18:22 ` [PULL 03/15] target/i386: " Richard Henderson
2021-10-13 18:22 ` [PULL 04/15] target/ppc: " Richard Henderson
2021-10-13 18:22 ` [PULL 05/15] target/s390x: " Richard Henderson
2021-10-13 18:22 ` Richard Henderson [this message]
2021-10-13 18:22 ` [PULL 07/15] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
2021-10-13 18:22 ` [PULL 08/15] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
2021-10-13 18:22 ` [PULL 09/15] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
2021-10-13 18:22 ` [PULL 10/15] target/mips: Use 8-byte memory ops " Richard Henderson
2021-10-13 18:22 ` [PULL 11/15] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
2021-10-13 18:22 ` [PULL 12/15] target/sparc: " Richard Henderson
2021-10-13 18:22 ` [PULL 13/15] target/arm: " Richard Henderson
2021-10-13 18:22 ` [PULL 14/15] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
2021-10-13 18:22 ` [PULL 15/15] tcg: Canonicalize alignment flags in MemOp Richard Henderson
2021-10-13 19:55 ` [PULL 00/15] tcg patch queue Richard Henderson

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