From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com,
fabien.portas@grenoble-inp.org
Subject: [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
Date: Wed, 13 Oct 2021 13:51:02 -0700 [thread overview]
Message-ID: <20211013205104.1031679-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211013205104.1031679-1-richard.henderson@linaro.org>
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+ tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+ return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--
2.25.1
next prev parent reply other threads:[~2021-10-13 21:08 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` Richard Henderson [this message]
2021-10-15 5:21 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
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