From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com,
fabien.portas@grenoble-inp.org
Subject: [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op
Date: Wed, 13 Oct 2021 13:50:58 -0700 [thread overview]
Message-ID: <20211013205104.1031679-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211013205104.1031679-1-richard.henderson@linaro.org>
We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less. Use a switch and explicitly
bound both SEW and SEQ for all cases.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index bbc5c93ef1..91fca4a2d1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -704,18 +704,20 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
- } else {
- if (s->sew == 3) {
- if (!is_32bit(s)) {
- fn = fnsd[seq];
- } else {
- /* Check done in amo_check(). */
- g_assert_not_reached();
- }
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
+ }
+
+ switch (s->sew) {
+ case 0 ... 2:
+ assert(seq < ARRAY_SIZE(fnsw));
+ fn = fnsw[seq];
+ break;
+ case 3:
+ /* XLEN check done in amo_check(). */
+ assert(seq < ARRAY_SIZE(fnsd));
+ fn = fnsd[seq];
+ break;
+ default:
+ g_assert_not_reached();
}
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
--
2.25.1
next prev parent reply other threads:[~2021-10-13 20:56 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` Richard Henderson [this message]
2021-10-14 5:55 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-14 8:26 ` LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-15 5:21 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
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