From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com,
fabien.portas@grenoble-inp.org
Subject: [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen
Date: Wed, 13 Oct 2021 13:50:59 -0700 [thread overview]
Message-ID: <20211013205104.1031679-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211013205104.1031679-1-richard.henderson@linaro.org>
In preparation for RV128, replace a simple predicate
with a more versatile test.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/translate.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7e7bb67d15..5724a62bb0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -91,16 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
}
#ifdef TARGET_RISCV32
-# define is_32bit(ctx) true
+#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
+#define get_xl(ctx) MXL_RV64
#else
-static inline bool is_32bit(DisasContext *ctx)
-{
- return ctx->xl == MXL_RV32;
-}
+#define get_xl(ctx) ((ctx)->xl)
#endif
+static inline int get_xlen(DisasContext *ctx)
+{
+ return 16 << get_xl(ctx);
+}
+
/* The word size for this operation. */
static inline int oper_len(DisasContext *ctx)
{
@@ -282,7 +284,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
- target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+ target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
@@ -341,16 +343,16 @@ EX_SH(12)
} \
} while (0)
-#define REQUIRE_32BIT(ctx) do { \
- if (!is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_32BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV32) { \
+ return false; \
+ } \
} while (0)
-#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_64BIT(ctx) do { \
+ if (get_xl(ctx) < MXL_RV64) { \
+ return false; \
+ } \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
--
2.25.1
next prev parent reply other threads:[~2021-10-13 21:00 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 20:50 [PATCH v2 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-13 20:50 ` [PATCH v2 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-13 20:50 ` [PATCH v2 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-13 20:50 ` [PATCH v2 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-14 7:52 ` LIU Zhiwei
2021-10-14 15:52 ` Richard Henderson
2021-10-15 5:01 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-14 7:08 ` LIU Zhiwei
2021-10-14 16:01 ` Richard Henderson
2021-10-15 5:05 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-14 8:20 ` LIU Zhiwei
2021-10-14 16:12 ` Richard Henderson
2021-10-15 12:37 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-14 5:54 ` LIU Zhiwei
2021-10-15 5:08 ` Alistair Francis
2021-10-13 20:50 ` [PATCH v2 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-14 5:55 ` LIU Zhiwei
2021-10-15 5:09 ` Alistair Francis
2021-10-13 20:50 ` Richard Henderson [this message]
2021-10-14 8:26 ` [PATCH v2 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen LIU Zhiwei
2021-10-15 5:11 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-14 8:40 ` LIU Zhiwei
2021-10-14 8:57 ` Frédéric Pétrot
2021-10-14 15:39 ` Richard Henderson
2021-10-15 5:19 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-13 20:51 ` [PATCH v2 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-15 5:21 ` Alistair Francis
2021-10-13 20:51 ` [PATCH v2 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-13 20:51 ` [PATCH v2 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
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