* [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:18 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
` (65 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Split out a function to adjust the raw signal pc into a
value that could be passed to cpu_restore_state.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Adjust pc in place; return MMUAccessType.
---
include/exec/exec-all.h | 10 ++++++++++
accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++----------------
2 files changed, 35 insertions(+), 16 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9d5987ba04..e54f8e5d65 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -663,6 +663,16 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
return addr;
}
+/**
+ * adjust_signal_pc:
+ * @pc: raw pc from the host signal ucontext_t.
+ * @is_write: host memory operation was write, or read-modify-write.
+ *
+ * Alter @pc as required for unwinding. Return the type of the
+ * guest memory access -- host reads may be for guest execution.
+ */
+MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
+
/**
* cpu_signal_handler
* @signum: host signal number
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e6bb29b42d..c02d509ec6 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -57,18 +57,11 @@ static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu,
cpu_loop_exit_noexc(cpu);
}
-/* 'pc' is the host PC at which the exception was raised. 'address' is
- the effective address of the memory exception. 'is_write' is 1 if a
- write caused the exception and otherwise 0'. 'old_set' is the
- signal set which should be restored */
-static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
- int is_write, sigset_t *old_set)
+/*
+ * Adjust the pc to pass to cpu_restore_state; return the memop type.
+ */
+MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
{
- CPUState *cpu = current_cpu;
- CPUClass *cc;
- unsigned long address = (unsigned long)info->si_addr;
- MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
-
switch (helper_retaddr) {
default:
/*
@@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* pointer into the generated code that will unwind to the
* correct guest pc.
*/
- pc = helper_retaddr;
+ *pc = helper_retaddr;
break;
case 0:
@@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* Therefore, adjust to compensate for what will be done later
* by cpu_restore_state_from_tb.
*/
- pc += GETPC_ADJ;
+ *pc += GETPC_ADJ;
break;
case 1:
@@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
*
* Like tb_gen_code, release the memory lock before cpu_loop_exit.
*/
- pc = 0;
- access_type = MMU_INST_FETCH;
mmap_unlock();
- break;
+ *pc = 0;
+ return MMU_INST_FETCH;
}
+ return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
+}
+
+/*
+ * 'pc' is the host PC at which the exception was raised.
+ * 'address' is the effective address of the memory exception.
+ * 'is_write' is 1 if a write caused the exception and otherwise 0.
+ * 'old_set' is the signal set which should be restored.
+ */
+static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
+ int is_write, sigset_t *old_set)
+{
+ CPUState *cpu = current_cpu;
+ CPUClass *cc;
+ unsigned long address = (unsigned long)info->si_addr;
+ MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
+
/* For synchronous signals we expect to be coming from the vCPU
* thread (so current_cpu should be valid) and either from running
* code or during translation which can fault as we cross pages.
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc
2021-10-15 4:09 ` [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc Richard Henderson
@ 2021-10-15 18:18 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:18 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 4469 bytes --]
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split out a function to adjust the raw signal pc into a
> value that could be passed to cpu_restore_state.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Adjust pc in place; return MMUAccessType.
> ---
> include/exec/exec-all.h | 10 ++++++++++
> accel/tcg/user-exec.c | 41 +++++++++++++++++++++++++----------------
> 2 files changed, 35 insertions(+), 16 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 9d5987ba04..e54f8e5d65 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -663,6 +663,16 @@ static inline tb_page_addr_t
> get_page_addr_code_hostp(CPUArchState *env,
> return addr;
> }
>
> +/**
> + * adjust_signal_pc:
> + * @pc: raw pc from the host signal ucontext_t.
> + * @is_write: host memory operation was write, or read-modify-write.
> + *
> + * Alter @pc as required for unwinding. Return the type of the
> + * guest memory access -- host reads may be for guest execution.
> + */
> +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
> +
> /**
> * cpu_signal_handler
> * @signum: host signal number
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index e6bb29b42d..c02d509ec6 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -57,18 +57,11 @@ static void QEMU_NORETURN
> cpu_exit_tb_from_sighandler(CPUState *cpu,
> cpu_loop_exit_noexc(cpu);
> }
>
> -/* 'pc' is the host PC at which the exception was raised. 'address' is
> - the effective address of the memory exception. 'is_write' is 1 if a
> - write caused the exception and otherwise 0'. 'old_set' is the
> - signal set which should be restored */
> -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
> - int is_write, sigset_t *old_set)
> +/*
> + * Adjust the pc to pass to cpu_restore_state; return the memop type.
> + */
> +MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
> {
> - CPUState *cpu = current_cpu;
> - CPUClass *cc;
> - unsigned long address = (unsigned long)info->si_addr;
> - MMUAccessType access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
> -
> switch (helper_retaddr) {
> default:
> /*
> @@ -77,7 +70,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> * pointer into the generated code that will unwind to the
> * correct guest pc.
> */
> - pc = helper_retaddr;
> + *pc = helper_retaddr;
> break;
>
> case 0:
> @@ -97,7 +90,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> * Therefore, adjust to compensate for what will be done later
> * by cpu_restore_state_from_tb.
> */
> - pc += GETPC_ADJ;
> + *pc += GETPC_ADJ;
> break;
>
> case 1:
> @@ -113,12 +106,28 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> *
> * Like tb_gen_code, release the memory lock before cpu_loop_exit.
> */
> - pc = 0;
> - access_type = MMU_INST_FETCH;
> mmap_unlock();
> - break;
> + *pc = 0;
> + return MMU_INST_FETCH;
> }
>
> + return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
> +}
> +
> +/*
> + * 'pc' is the host PC at which the exception was raised.
> + * 'address' is the effective address of the memory exception.
> + * 'is_write' is 1 if a write caused the exception and otherwise 0.
> + * 'old_set' is the signal set which should be restored.
> + */
> +static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
> + int is_write, sigset_t *old_set)
> +{
> + CPUState *cpu = current_cpu;
> + CPUClass *cc;
> + unsigned long address = (unsigned long)info->si_addr;
> + MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
> +
> /* For synchronous signals we expect to be coming from the vCPU
> * thread (so current_cpu should be valid) and either from running
> * code or during translation which can fault as we cross pages.
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 5614 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-10-15 4:09 ` [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 4:09 ` [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
` (64 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Currently there are only two places that require we reset this
value before exiting to the main loop, but that will change.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cpu-exec.c | 3 ++-
accel/tcg/user-exec.c | 2 --
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5fd1ed3422..410588d08a 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -451,6 +451,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
* memory.
*/
#ifndef CONFIG_SOFTMMU
+ clear_helper_retaddr();
tcg_debug_assert(!have_mmap_lock());
#endif
if (qemu_mutex_iothread_locked()) {
@@ -460,7 +461,6 @@ void cpu_exec_step_atomic(CPUState *cpu)
qemu_plugin_disable_mem_helpers(cpu);
}
-
/*
* As we start the exclusive region before codegen we must still
* be in the region if we longjump out of either the codegen or
@@ -905,6 +905,7 @@ int cpu_exec(CPUState *cpu)
#endif
#ifndef CONFIG_SOFTMMU
+ clear_helper_retaddr();
tcg_debug_assert(!have_mmap_lock());
#endif
if (qemu_mutex_iothread_locked()) {
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index c02d509ec6..3f3e793b7b 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -175,7 +175,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* currently executing TB was modified and must be exited
* immediately. Clear helper_retaddr for next execution.
*/
- clear_helper_retaddr();
cpu_exit_tb_from_sighandler(cpu, old_set);
/* NORETURN */
@@ -193,7 +192,6 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
* an exception. Undo signal and retaddr state prior to longjmp.
*/
sigprocmask(SIG_SETMASK, old_set, NULL);
- clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
2021-10-15 4:09 ` [PATCH v5 01/67] accel/tcg: Split out adjust_signal_pc Richard Henderson
2021-10-15 4:09 ` [PATCH v5 02/67] accel/tcg: Move clear_helper_retaddr to cpu loop Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:19 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
` (63 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
This is the major portion of handle_cpu_signal which is specific
to tcg, handling the page protections for the translations.
Most of the rest will migrate to linux-user/ shortly.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Pass guest address to handle_sigsegv_accerr_write.
---
include/exec/exec-all.h | 12 +++++
accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++----------------
2 files changed, 74 insertions(+), 41 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index e54f8e5d65..5f94d799aa 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -673,6 +673,18 @@ static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
*/
MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
+/**
+ * handle_sigsegv_accerr_write:
+ * @cpu: the cpu context
+ * @old_set: the sigset_t from the signal ucontext_t
+ * @host_pc: the host pc, adjusted for the signal
+ * @host_addr: the host address of the fault
+ *
+ * Return true if the write fault has been handled, and should be re-tried.
+ */
+bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
+ uintptr_t host_pc, abi_ptr guest_addr);
+
/**
* cpu_signal_handler
* @signum: host signal number
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3f3e793b7b..cb63e528c5 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
}
+/**
+ * handle_sigsegv_accerr_write:
+ * @cpu: the cpu context
+ * @old_set: the sigset_t from the signal ucontext_t
+ * @host_pc: the host pc, adjusted for the signal
+ * @guest_addr: the guest address of the fault
+ *
+ * Return true if the write fault has been handled, and should be re-tried.
+ *
+ * Note that it is important that we don't call page_unprotect() unless
+ * this is really a "write to nonwriteable page" fault, because
+ * page_unprotect() assumes that if it is called for an access to
+ * a page that's writeable this means we had two threads racing and
+ * another thread got there first and already made the page writeable;
+ * so we will retry the access. If we were to call page_unprotect()
+ * for some other kind of fault that should really be passed to the
+ * guest, we'd end up in an infinite loop of retrying the faulting access.
+ */
+bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
+ uintptr_t host_pc, abi_ptr guest_addr)
+{
+ switch (page_unprotect(guest_addr, host_pc)) {
+ case 0:
+ /*
+ * Fault not caused by a page marked unwritable to protect
+ * cached translations, must be the guest binary's problem.
+ */
+ return false;
+ case 1:
+ /*
+ * Fault caused by protection of cached translation; TBs
+ * invalidated, so resume execution. Retain helper_retaddr
+ * for a possible second fault.
+ */
+ return true;
+ case 2:
+ /*
+ * Fault caused by protection of cached translation, and the
+ * currently executing TB was modified and must be exited
+ * immediately. Clear helper_retaddr for next execution.
+ */
+ cpu_exit_tb_from_sighandler(cpu, old_set);
+ /* NORETURN */
+ default:
+ g_assert_not_reached();
+ }
+}
+
/*
* 'pc' is the host PC at which the exception was raised.
* 'address' is the effective address of the memory exception.
@@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
{
CPUState *cpu = current_cpu;
CPUClass *cc;
- unsigned long address = (unsigned long)info->si_addr;
+ unsigned long host_addr = (unsigned long)info->si_addr;
MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
+ abi_ptr guest_addr;
/* For synchronous signals we expect to be coming from the vCPU
* thread (so current_cpu should be valid) and either from running
@@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
#if defined(DEBUG_SIGNAL)
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
- pc, address, is_write, *(unsigned long *)old_set);
+ pc, host_addr, is_write, *(unsigned long *)old_set);
#endif
- /* XXX: locking issue */
- /* Note that it is important that we don't call page_unprotect() unless
- * this is really a "write to nonwriteable page" fault, because
- * page_unprotect() assumes that if it is called for an access to
- * a page that's writeable this means we had two threads racing and
- * another thread got there first and already made the page writeable;
- * so we will retry the access. If we were to call page_unprotect()
- * for some other kind of fault that should really be passed to the
- * guest, we'd end up in an infinite loop of retrying the faulting
- * access.
- */
- if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR &&
- h2g_valid(address)) {
- switch (page_unprotect(h2g(address), pc)) {
- case 0:
- /* Fault not caused by a page marked unwritable to protect
- * cached translations, must be the guest binary's problem.
- */
- break;
- case 1:
- /* Fault caused by protection of cached translation; TBs
- * invalidated, so resume execution. Retain helper_retaddr
- * for a possible second fault.
- */
- return 1;
- case 2:
- /* Fault caused by protection of cached translation, and the
- * currently executing TB was modified and must be exited
- * immediately. Clear helper_retaddr for next execution.
- */
- cpu_exit_tb_from_sighandler(cpu, old_set);
- /* NORETURN */
-
- default:
- g_assert_not_reached();
- }
- }
/* Convert forcefully to guest address space, invalid addresses
are still valid segv ones */
- address = h2g_nocheck(address);
+ guest_addr = h2g_nocheck(host_addr);
+
+ /* XXX: locking issue */
+ if (is_write &&
+ info->si_signo == SIGSEGV &&
+ info->si_code == SEGV_ACCERR &&
+ h2g_valid(host_addr) &&
+ handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
+ return 1;
+ }
/*
* There is no way the target can handle this other than raising
@@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
sigprocmask(SIG_SETMASK, old_set, NULL);
cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
+ cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write
2021-10-15 4:09 ` [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
@ 2021-10-15 18:19 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:19 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 7730 bytes --]
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> This is the major portion of handle_cpu_signal which is specific
> to tcg, handling the page protections for the translations.
> Most of the rest will migrate to linux-user/ shortly.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Pass guest address to handle_sigsegv_accerr_write.
> ---
> include/exec/exec-all.h | 12 +++++
> accel/tcg/user-exec.c | 103 ++++++++++++++++++++++++----------------
> 2 files changed, 74 insertions(+), 41 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index e54f8e5d65..5f94d799aa 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -673,6 +673,18 @@ static inline tb_page_addr_t
> get_page_addr_code_hostp(CPUArchState *env,
> */
> MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
>
> +/**
> + * handle_sigsegv_accerr_write:
> + * @cpu: the cpu context
> + * @old_set: the sigset_t from the signal ucontext_t
> + * @host_pc: the host pc, adjusted for the signal
> + * @host_addr: the host address of the fault
> + *
> + * Return true if the write fault has been handled, and should be
> re-tried.
> + */
> +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
> + uintptr_t host_pc, abi_ptr guest_addr);
> +
> /**
> * cpu_signal_handler
> * @signum: host signal number
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 3f3e793b7b..cb63e528c5 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -114,6 +114,54 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool
> is_write)
> return is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
> }
>
> +/**
> + * handle_sigsegv_accerr_write:
> + * @cpu: the cpu context
> + * @old_set: the sigset_t from the signal ucontext_t
> + * @host_pc: the host pc, adjusted for the signal
> + * @guest_addr: the guest address of the fault
> + *
> + * Return true if the write fault has been handled, and should be
> re-tried.
> + *
> + * Note that it is important that we don't call page_unprotect() unless
> + * this is really a "write to nonwriteable page" fault, because
> + * page_unprotect() assumes that if it is called for an access to
> + * a page that's writeable this means we had two threads racing and
> + * another thread got there first and already made the page writeable;
> + * so we will retry the access. If we were to call page_unprotect()
> + * for some other kind of fault that should really be passed to the
> + * guest, we'd end up in an infinite loop of retrying the faulting access.
> + */
> +bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
> + uintptr_t host_pc, abi_ptr guest_addr)
> +{
> + switch (page_unprotect(guest_addr, host_pc)) {
> + case 0:
> + /*
> + * Fault not caused by a page marked unwritable to protect
> + * cached translations, must be the guest binary's problem.
> + */
> + return false;
> + case 1:
> + /*
> + * Fault caused by protection of cached translation; TBs
> + * invalidated, so resume execution. Retain helper_retaddr
> + * for a possible second fault.
> + */
> + return true;
> + case 2:
> + /*
> + * Fault caused by protection of cached translation, and the
> + * currently executing TB was modified and must be exited
> + * immediately. Clear helper_retaddr for next execution.
> + */
> + cpu_exit_tb_from_sighandler(cpu, old_set);
> + /* NORETURN */
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> /*
> * 'pc' is the host PC at which the exception was raised.
> * 'address' is the effective address of the memory exception.
> @@ -125,8 +173,9 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> {
> CPUState *cpu = current_cpu;
> CPUClass *cc;
> - unsigned long address = (unsigned long)info->si_addr;
> + unsigned long host_addr = (unsigned long)info->si_addr;
> MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
> + abi_ptr guest_addr;
>
> /* For synchronous signals we expect to be coming from the vCPU
> * thread (so current_cpu should be valid) and either from running
> @@ -143,49 +192,21 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
>
> #if defined(DEBUG_SIGNAL)
> printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
> - pc, address, is_write, *(unsigned long *)old_set);
> + pc, host_addr, is_write, *(unsigned long *)old_set);
> #endif
> - /* XXX: locking issue */
> - /* Note that it is important that we don't call page_unprotect()
> unless
> - * this is really a "write to nonwriteable page" fault, because
> - * page_unprotect() assumes that if it is called for an access to
> - * a page that's writeable this means we had two threads racing and
> - * another thread got there first and already made the page writeable;
> - * so we will retry the access. If we were to call page_unprotect()
> - * for some other kind of fault that should really be passed to the
> - * guest, we'd end up in an infinite loop of retrying the faulting
> - * access.
> - */
> - if (is_write && info->si_signo == SIGSEGV && info->si_code ==
> SEGV_ACCERR &&
> - h2g_valid(address)) {
> - switch (page_unprotect(h2g(address), pc)) {
> - case 0:
> - /* Fault not caused by a page marked unwritable to protect
> - * cached translations, must be the guest binary's problem.
> - */
> - break;
> - case 1:
> - /* Fault caused by protection of cached translation; TBs
> - * invalidated, so resume execution. Retain helper_retaddr
> - * for a possible second fault.
> - */
> - return 1;
> - case 2:
> - /* Fault caused by protection of cached translation, and the
> - * currently executing TB was modified and must be exited
> - * immediately. Clear helper_retaddr for next execution.
> - */
> - cpu_exit_tb_from_sighandler(cpu, old_set);
> - /* NORETURN */
> -
> - default:
> - g_assert_not_reached();
> - }
> - }
>
> /* Convert forcefully to guest address space, invalid addresses
> are still valid segv ones */
> - address = h2g_nocheck(address);
> + guest_addr = h2g_nocheck(host_addr);
> +
> + /* XXX: locking issue */
> + if (is_write &&
> + info->si_signo == SIGSEGV &&
> + info->si_code == SEGV_ACCERR &&
> + h2g_valid(host_addr) &&
> + handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
> + return 1;
> + }
>
> /*
> * There is no way the target can handle this other than raising
> @@ -194,7 +215,7 @@ static inline int handle_cpu_signal(uintptr_t pc,
> siginfo_t *info,
> sigprocmask(SIG_SETMASK, old_set, NULL);
>
> cc = CPU_GET_CLASS(cpu);
> - cc->tcg_ops->tlb_fill(cpu, address, 0, access_type,
> + cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
> MMU_USER_IDX, false, pc);
> g_assert_not_reached();
> }
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 9323 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (2 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 03/67] accel/tcg: Split out handle_sigsegv_accerr_write Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:20 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
` (62 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Remove the comment about siglongjmp. We do use sigsetjmp
in the main cpu loop, but we do not save the signal mask
as most exits from the cpu loop do not require them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index cb63e528c5..744af19397 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr;
//#define DEBUG_SIGNAL
-/* exit the current TB from a signal handler. The host registers are
- restored in a state compatible with the CPU emulator
- */
-static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu,
- sigset_t *old_set)
-{
- /* XXX: use siglongjmp ? */
- sigprocmask(SIG_SETMASK, old_set, NULL);
- cpu_loop_exit_noexc(cpu);
-}
-
/*
* Adjust the pc to pass to cpu_restore_state; return the memop type.
*/
@@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
* currently executing TB was modified and must be exited
* immediately. Clear helper_retaddr for next execution.
*/
- cpu_exit_tb_from_sighandler(cpu, old_set);
+ sigprocmask(SIG_SETMASK, old_set, NULL);
+ cpu_loop_exit_noexc(cpu);
/* NORETURN */
default:
g_assert_not_reached();
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller
2021-10-15 4:09 ` [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
@ 2021-10-15 18:20 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 1713 bytes --]
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Remove the comment about siglongjmp. We do use sigsetjmp
> in the main cpu loop, but we do not save the signal mask
> as most exits from the cpu loop do not require them.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/user-exec.c | 14 ++------------
> 1 file changed, 2 insertions(+), 12 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index cb63e528c5..744af19397 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -46,17 +46,6 @@ __thread uintptr_t helper_retaddr;
>
> //#define DEBUG_SIGNAL
>
> -/* exit the current TB from a signal handler. The host registers are
> - restored in a state compatible with the CPU emulator
> - */
> -static void QEMU_NORETURN cpu_exit_tb_from_sighandler(CPUState *cpu,
> - sigset_t *old_set)
> -{
> - /* XXX: use siglongjmp ? */
> - sigprocmask(SIG_SETMASK, old_set, NULL);
> - cpu_loop_exit_noexc(cpu);
> -}
> -
> /*
> * Adjust the pc to pass to cpu_restore_state; return the memop type.
> */
> @@ -155,7 +144,8 @@ bool handle_sigsegv_accerr_write(CPUState *cpu,
> sigset_t *old_set,
> * currently executing TB was modified and must be exited
> * immediately. Clear helper_retaddr for next execution.
> */
> - cpu_exit_tb_from_sighandler(cpu, old_set);
> + sigprocmask(SIG_SETMASK, old_set, NULL);
> + cpu_loop_exit_noexc(cpu);
> /* NORETURN */
> default:
> g_assert_not_reached();
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 2575 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (3 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 04/67] accel/tcg: Fold cpu_exit_tb_from_sighandler into caller Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:21 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV Richard Henderson
` (61 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
The existing code for safe-syscall.inc.S will compile
without change for riscv32 and riscv64. We may also
drop the meson.build stanza that merges them for tcg/.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 8 ++------
meson.build | 4 +---
linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++--
linux-user/host/riscv32/hostdep.h | 11 -----------
linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0
5 files changed, 5 insertions(+), 22 deletions(-)
rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%)
delete mode 100644 linux-user/host/riscv32/hostdep.h
rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%)
diff --git a/configure b/configure
index 039467c04b..d57ad58342 100755
--- a/configure
+++ b/configure
@@ -570,11 +570,7 @@ elif check_define __s390__ ; then
cpu="s390"
fi
elif check_define __riscv ; then
- if check_define _LP64 ; then
- cpu="riscv64"
- else
- cpu="riscv32"
- fi
+ cpu="riscv"
elif check_define __arm__ ; then
cpu="arm"
elif check_define __aarch64__ ; then
@@ -587,7 +583,7 @@ ARCH=
# Normalise host CPU name and set ARCH.
# Note that this case should only have supported host CPUs, not guests.
case "$cpu" in
- ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64)
+ ppc|ppc64|s390x|sparc64|x32|riscv)
;;
ppc64le)
ARCH="ppc64"
diff --git a/meson.build b/meson.build
index 6b7487b725..1a8fc2c4e0 100644
--- a/meson.build
+++ b/meson.build
@@ -52,7 +52,7 @@ have_block = have_system or have_tools
python = import('python').find_installation()
supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin', 'sunos', 'linux']
-supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86', 'x86_64',
+supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
cpu = host_machine.cpu_family()
@@ -342,8 +342,6 @@ if not get_option('tcg').disabled()
tcg_arch = 'i386'
elif config_host['ARCH'] == 'ppc64'
tcg_arch = 'ppc'
- elif config_host['ARCH'] in ['riscv32', 'riscv64']
- tcg_arch = 'riscv'
endif
add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch,
language: ['c', 'cpp', 'objc'])
diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv/hostdep.h
similarity index 94%
rename from linux-user/host/riscv64/hostdep.h
rename to linux-user/host/riscv/hostdep.h
index 865f0fb9ff..2ba07456ae 100644
--- a/linux-user/host/riscv64/hostdep.h
+++ b/linux-user/host/riscv/hostdep.h
@@ -5,8 +5,8 @@
* See the COPYING file in the top-level directory.
*/
-#ifndef RISCV64_HOSTDEP_H
-#define RISCV64_HOSTDEP_H
+#ifndef RISCV_HOSTDEP_H
+#define RISCV_HOSTDEP_H
/* We have a safe-syscall.inc.S */
#define HAVE_SAFE_SYSCALL
diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h
deleted file mode 100644
index adf9edbf2d..0000000000
--- a/linux-user/host/riscv32/hostdep.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * hostdep.h : things which are dependent on the host architecture
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef RISCV32_HOSTDEP_H
-#define RISCV32_HOSTDEP_H
-
-#endif
diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S
similarity index 100%
rename from linux-user/host/riscv64/safe-syscall.inc.S
rename to linux-user/host/riscv/safe-syscall.inc.S
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures
2021-10-15 4:09 ` [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
@ 2021-10-15 18:21 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:21 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, Philippe Mathieu-Daudé, Alex Bennée,
QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 4258 bytes --]
On Thu, Oct 14, 2021 at 10:10 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> The existing code for safe-syscall.inc.S will compile
> without change for riscv32 and riscv64. We may also
> drop the meson.build stanza that merges them for tcg/.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> configure | 8 ++------
> meson.build | 4 +---
> linux-user/host/{riscv64 => riscv}/hostdep.h | 4 ++--
> linux-user/host/riscv32/hostdep.h | 11 -----------
> linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S | 0
> 5 files changed, 5 insertions(+), 22 deletions(-)
> rename linux-user/host/{riscv64 => riscv}/hostdep.h (94%)
> delete mode 100644 linux-user/host/riscv32/hostdep.h
> rename linux-user/host/{riscv64 => riscv}/safe-syscall.inc.S (100%)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/configure b/configure
> index 039467c04b..d57ad58342 100755
> --- a/configure
> +++ b/configure
> @@ -570,11 +570,7 @@ elif check_define __s390__ ; then
> cpu="s390"
> fi
> elif check_define __riscv ; then
> - if check_define _LP64 ; then
> - cpu="riscv64"
> - else
> - cpu="riscv32"
> - fi
> + cpu="riscv"
> elif check_define __arm__ ; then
> cpu="arm"
> elif check_define __aarch64__ ; then
> @@ -587,7 +583,7 @@ ARCH=
> # Normalise host CPU name and set ARCH.
> # Note that this case should only have supported host CPUs, not guests.
> case "$cpu" in
> - ppc|ppc64|s390x|sparc64|x32|riscv32|riscv64)
> + ppc|ppc64|s390x|sparc64|x32|riscv)
> ;;
> ppc64le)
> ARCH="ppc64"
> diff --git a/meson.build b/meson.build
> index 6b7487b725..1a8fc2c4e0 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -52,7 +52,7 @@ have_block = have_system or have_tools
> python = import('python').find_installation()
>
> supported_oses = ['windows', 'freebsd', 'netbsd', 'openbsd', 'darwin',
> 'sunos', 'linux']
> -supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv32', 'riscv64', 'x86',
> 'x86_64',
> +supported_cpus = ['ppc', 'ppc64', 's390x', 'riscv', 'x86', 'x86_64',
> 'arm', 'aarch64', 'mips', 'mips64', 'sparc', 'sparc64']
>
> cpu = host_machine.cpu_family()
> @@ -342,8 +342,6 @@ if not get_option('tcg').disabled()
> tcg_arch = 'i386'
> elif config_host['ARCH'] == 'ppc64'
> tcg_arch = 'ppc'
> - elif config_host['ARCH'] in ['riscv32', 'riscv64']
> - tcg_arch = 'riscv'
> endif
> add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' /
> tcg_arch,
> language: ['c', 'cpp', 'objc'])
> diff --git a/linux-user/host/riscv64/hostdep.h
> b/linux-user/host/riscv/hostdep.h
> similarity index 94%
> rename from linux-user/host/riscv64/hostdep.h
> rename to linux-user/host/riscv/hostdep.h
> index 865f0fb9ff..2ba07456ae 100644
> --- a/linux-user/host/riscv64/hostdep.h
> +++ b/linux-user/host/riscv/hostdep.h
> @@ -5,8 +5,8 @@
> * See the COPYING file in the top-level directory.
> */
>
> -#ifndef RISCV64_HOSTDEP_H
> -#define RISCV64_HOSTDEP_H
> +#ifndef RISCV_HOSTDEP_H
> +#define RISCV_HOSTDEP_H
>
> /* We have a safe-syscall.inc.S */
> #define HAVE_SAFE_SYSCALL
> diff --git a/linux-user/host/riscv32/hostdep.h
> b/linux-user/host/riscv32/hostdep.h
> deleted file mode 100644
> index adf9edbf2d..0000000000
> --- a/linux-user/host/riscv32/hostdep.h
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -/*
> - * hostdep.h : things which are dependent on the host architecture
> - *
> - * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> - * See the COPYING file in the top-level directory.
> - */
> -
> -#ifndef RISCV32_HOSTDEP_H
> -#define RISCV32_HOSTDEP_H
> -
> -#endif
> diff --git a/linux-user/host/riscv64/safe-syscall.inc.S
> b/linux-user/host/riscv/safe-syscall.inc.S
> similarity index 100%
> rename from linux-user/host/riscv64/safe-syscall.inc.S
> rename to linux-user/host/riscv/safe-syscall.inc.S
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 5732 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (4 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 05/67] configure: Merge riscv32 and riscv64 host architectures Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 4:09 ` [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h Richard Henderson
` (60 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
Add stub host-signal.h for all linux-user hosts.
Add new code replacing cpu_signal_handler.
Full migration will happen one host at a time.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/aarch64/host-signal.h | 1 +
linux-user/host/arm/host-signal.h | 1 +
linux-user/host/i386/host-signal.h | 1 +
linux-user/host/mips/host-signal.h | 1 +
linux-user/host/ppc/host-signal.h | 1 +
linux-user/host/ppc64/host-signal.h | 1 +
linux-user/host/riscv/host-signal.h | 1 +
linux-user/host/s390/host-signal.h | 1 +
linux-user/host/s390x/host-signal.h | 1 +
linux-user/host/sparc/host-signal.h | 1 +
linux-user/host/sparc64/host-signal.h | 1 +
linux-user/host/x32/host-signal.h | 1 +
linux-user/host/x86_64/host-signal.h | 1 +
linux-user/signal.c | 109 ++++++++++++++++++++++----
14 files changed, 106 insertions(+), 16 deletions(-)
create mode 100644 linux-user/host/aarch64/host-signal.h
create mode 100644 linux-user/host/arm/host-signal.h
create mode 100644 linux-user/host/i386/host-signal.h
create mode 100644 linux-user/host/mips/host-signal.h
create mode 100644 linux-user/host/ppc/host-signal.h
create mode 100644 linux-user/host/ppc64/host-signal.h
create mode 100644 linux-user/host/riscv/host-signal.h
create mode 100644 linux-user/host/s390/host-signal.h
create mode 100644 linux-user/host/s390x/host-signal.h
create mode 100644 linux-user/host/sparc/host-signal.h
create mode 100644 linux-user/host/sparc64/host-signal.h
create mode 100644 linux-user/host/x32/host-signal.h
create mode 100644 linux-user/host/x86_64/host-signal.h
diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/aarch64/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/arm/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/i386/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/mips/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/ppc/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/ppc64/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/riscv/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/s390/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/s390x/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/sparc/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/sparc64/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/x32/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h
new file mode 100644
index 0000000000..f4b4d65031
--- /dev/null
+++ b/linux-user/host/x86_64/host-signal.h
@@ -0,0 +1 @@
+#define HOST_SIGNAL_PLACEHOLDER
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 14d8fdfde1..6900acb122 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "exec/gdbstub.h"
+#include "hw/core/tcg-cpu-ops.h"
#include <sys/ucontext.h>
#include <sys/resource.h>
@@ -29,6 +30,7 @@
#include "loader.h"
#include "trace.h"
#include "signal-common.h"
+#include "host-signal.h"
static struct target_sigaction sigact_table[TARGET_NSIG];
@@ -769,41 +771,116 @@ static inline void rewind_if_in_safe_syscall(void *puc)
}
#endif
-static void host_signal_handler(int host_signum, siginfo_t *info,
- void *puc)
+static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
{
CPUArchState *env = thread_cpu->env_ptr;
CPUState *cpu = env_cpu(env);
TaskState *ts = cpu->opaque;
-
- int sig;
target_siginfo_t tinfo;
ucontext_t *uc = puc;
struct emulated_sigtable *k;
+ int guest_sig;
+#ifdef HOST_SIGNAL_PLACEHOLDER
/* the CPU emulator uses some host signals to detect exceptions,
we forward to it some signals */
- if ((host_signum == SIGSEGV || host_signum == SIGBUS)
+ if ((host_sig == SIGSEGV || host_sig == SIGBUS)
&& info->si_code > 0) {
- if (cpu_signal_handler(host_signum, info, puc))
+ if (cpu_signal_handler(host_sig, info, puc)) {
return;
+ }
}
+#else
+ uintptr_t pc = 0;
+ bool sync_sig = false;
+
+ /*
+ * Non-spoofed SIGSEGV and SIGBUS are synchronous, and need special
+ * handling wrt signal blocking and unwinding.
+ */
+ if ((host_sig == SIGSEGV || host_sig == SIGBUS) && info->si_code > 0) {
+ MMUAccessType access_type;
+ uintptr_t host_addr;
+ abi_ptr guest_addr;
+ bool is_write;
+
+ host_addr = (uintptr_t)info->si_addr;
+
+ /*
+ * Convert forcefully to guest address space: addresses outside
+ * reserved_va are still valid to report via SEGV_MAPERR.
+ */
+ guest_addr = h2g_nocheck(host_addr);
+
+ pc = host_signal_pc(uc);
+ is_write = host_signal_write(info, uc);
+ access_type = adjust_signal_pc(&pc, is_write);
+
+ if (host_sig == SIGSEGV) {
+ const struct TCGCPUOps *tcg_ops;
+
+ if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) {
+ /* If this was a write to a TB protected page, restart. */
+ if (is_write &&
+ handle_sigsegv_accerr_write(cpu, &uc->uc_sigmask,
+ pc, guest_addr)) {
+ return;
+ }
+
+ /*
+ * With reserved_va, the whole address space is PROT_NONE,
+ * which means that we may get ACCERR when we want MAPERR.
+ */
+ if (page_get_flags(guest_addr) & PAGE_VALID) {
+ /* maperr = false; */
+ } else {
+ info->si_code = SEGV_MAPERR;
+ }
+ }
+
+ sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
+
+ tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+ tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
+ MMU_USER_IDX, false, pc);
+ g_assert_not_reached();
+ } else {
+ sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
+ }
+
+ sync_sig = true;
+ }
+#endif
/* get target signal number */
- sig = host_to_target_signal(host_signum);
- if (sig < 1 || sig > TARGET_NSIG)
+ guest_sig = host_to_target_signal(host_sig);
+ if (guest_sig < 1 || guest_sig > TARGET_NSIG) {
return;
- trace_user_host_signal(env, host_signum, sig);
+ }
+ trace_user_host_signal(env, host_sig, guest_sig);
+
+ host_to_target_siginfo_noswap(&tinfo, info);
+ k = &ts->sigtab[guest_sig - 1];
+ k->info = tinfo;
+ k->pending = guest_sig;
+ ts->signal_pending = 1;
+
+#ifndef HOST_SIGNAL_PLACEHOLDER
+ /*
+ * For synchronous signals, unwind the cpu state to the faulting
+ * insn and then exit back to the main loop so that the signal
+ * is delivered immediately.
+ */
+ if (sync_sig) {
+ cpu->exception_index = EXCP_INTERRUPT;
+ cpu_loop_exit_restore(cpu, pc);
+ }
+#endif
rewind_if_in_safe_syscall(puc);
- host_to_target_siginfo_noswap(&tinfo, info);
- k = &ts->sigtab[sig - 1];
- k->info = tinfo;
- k->pending = sig;
- ts->signal_pending = 1;
-
- /* Block host signals until target signal handler entered. We
+ /*
+ * Block host signals until target signal handler entered. We
* can't block SIGSEGV or SIGBUS while we're executing guest
* code in case the guest code provokes one in the window between
* now and it getting out to the main loop. Signals will be
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (5 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 06/67] linux-user: Reorg handling for SIGSEGV Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:26 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 08/67] linux-user/host/ppc: " Richard Henderson
` (59 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/i386/host-signal.h | 25 ++++-
linux-user/host/x32/host-signal.h | 2 +-
linux-user/host/x86_64/host-signal.h | 25 ++++-
accel/tcg/user-exec.c | 136 +--------------------------
4 files changed, 50 insertions(+), 138 deletions(-)
diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h
index f4b4d65031..ccbbee5082 100644
--- a/linux-user/host/i386/host-signal.h
+++ b/linux-user/host/i386/host-signal.h
@@ -1 +1,24 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef I386_HOST_SIGNAL_H
+#define I386_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.gregs[REG_EIP];
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe
+ && (uc->uc_mcontext.gregs[REG_ERR] & 0x2);
+}
+
+#endif
diff --git a/linux-user/host/x32/host-signal.h b/linux-user/host/x32/host-signal.h
index f4b4d65031..26800591d3 100644
--- a/linux-user/host/x32/host-signal.h
+++ b/linux-user/host/x32/host-signal.h
@@ -1 +1 @@
-#define HOST_SIGNAL_PLACEHOLDER
+#include "../x86_64/host-signal.h"
diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h
index f4b4d65031..883d2fcf65 100644
--- a/linux-user/host/x86_64/host-signal.h
+++ b/linux-user/host/x86_64/host-signal.h
@@ -1 +1,24 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef X86_64_HOST_SIGNAL_H
+#define X86_64_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.gregs[REG_RIP];
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe
+ && (uc->uc_mcontext.gregs[REG_ERR] & 0x2);
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 744af19397..474cb9cf82 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -29,19 +29,6 @@
#include "trace/trace-root.h"
#include "internal.h"
-#undef EAX
-#undef ECX
-#undef EDX
-#undef EBX
-#undef ESP
-#undef EBP
-#undef ESI
-#undef EDI
-#undef EIP
-#ifdef __linux__
-#include <sys/ucontext.h>
-#endif
-
__thread uintptr_t helper_retaddr;
//#define DEBUG_SIGNAL
@@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__i386__)
-
-#if defined(__NetBSD__)
-#include <ucontext.h>
-#include <machine/trap.h>
-
-#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
-#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
-#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#elif defined(__FreeBSD__) || defined(__DragonFly__)
-#include <ucontext.h>
-#include <machine/trap.h>
-
-#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
-#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
-#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#elif defined(__OpenBSD__)
-#include <machine/trap.h>
-#define EIP_sig(context) ((context)->sc_eip)
-#define TRAP_sig(context) ((context)->sc_trapno)
-#define ERROR_sig(context) ((context)->sc_err)
-#define MASK_sig(context) ((context)->sc_mask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#else
-#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
-#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
-#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP 0xe
-#endif
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
-#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
- ucontext_t *uc = puc;
-#elif defined(__OpenBSD__)
- struct sigcontext *uc = puc;
-#else
- ucontext_t *uc = puc;
-#endif
- unsigned long pc;
- int trapno;
-
-#ifndef REG_EIP
-/* for glibc 2.1 */
-#define REG_EIP EIP
-#define REG_ERR ERR
-#define REG_TRAPNO TRAPNO
-#endif
- pc = EIP_sig(uc);
- trapno = TRAP_sig(uc);
- return handle_cpu_signal(pc, info,
- trapno == PAGE_FAULT_TRAP ?
- (ERROR_sig(uc) >> 1) & 1 : 0,
- &MASK_sig(uc));
-}
-
-#elif defined(__x86_64__)
-
-#ifdef __NetBSD__
-#include <machine/trap.h>
-#define PC_sig(context) _UC_MACHINE_PC(context)
-#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
-#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#elif defined(__OpenBSD__)
-#include <machine/trap.h>
-#define PC_sig(context) ((context)->sc_rip)
-#define TRAP_sig(context) ((context)->sc_trapno)
-#define ERROR_sig(context) ((context)->sc_err)
-#define MASK_sig(context) ((context)->sc_mask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#elif defined(__FreeBSD__) || defined(__DragonFly__)
-#include <ucontext.h>
-#include <machine/trap.h>
-
-#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
-#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
-#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP T_PAGEFLT
-#else
-#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
-#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
-#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
-#define MASK_sig(context) ((context)->uc_sigmask)
-#define PAGE_FAULT_TRAP 0xe
-#endif
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- unsigned long pc;
-#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
- ucontext_t *uc = puc;
-#elif defined(__OpenBSD__)
- struct sigcontext *uc = puc;
-#else
- ucontext_t *uc = puc;
-#endif
-
- pc = PC_sig(uc);
- return handle_cpu_signal(pc, info,
- TRAP_sig(uc) == PAGE_FAULT_TRAP ?
- (ERROR_sig(uc) >> 1) & 1 : 0,
- &MASK_sig(uc));
-}
-
-#elif defined(_ARCH_PPC)
+#if defined(_ARCH_PPC)
/***********************************************************************
* signal context platform-specific definitions
@@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo,
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
-
-#else
-
-#error host CPU specific signal handler needed
-
#endif
/* The softmmu versions of these helpers are in cputlb.c. */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h
2021-10-15 4:09 ` [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h Richard Henderson
@ 2021-10-15 18:26 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 8474 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/i386/host-signal.h | 25 ++++-
> linux-user/host/x32/host-signal.h | 2 +-
> linux-user/host/x86_64/host-signal.h | 25 ++++-
> accel/tcg/user-exec.c | 136 +--------------------------
> 4 files changed, 50 insertions(+), 138 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Though I've not pulled this into bsd-user to see how it affects me,
so I may come to regret this :)
Warner
> diff --git a/linux-user/host/i386/host-signal.h
> b/linux-user/host/i386/host-signal.h
> index f4b4d65031..ccbbee5082 100644
> --- a/linux-user/host/i386/host-signal.h
> +++ b/linux-user/host/i386/host-signal.h
> @@ -1 +1,24 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef I386_HOST_SIGNAL_H
> +#define I386_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.gregs[REG_EIP];
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe
> + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2);
> +}
> +
> +#endif
> diff --git a/linux-user/host/x32/host-signal.h
> b/linux-user/host/x32/host-signal.h
> index f4b4d65031..26800591d3 100644
> --- a/linux-user/host/x32/host-signal.h
> +++ b/linux-user/host/x32/host-signal.h
> @@ -1 +1 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +#include "../x86_64/host-signal.h"
> diff --git a/linux-user/host/x86_64/host-signal.h
> b/linux-user/host/x86_64/host-signal.h
> index f4b4d65031..883d2fcf65 100644
> --- a/linux-user/host/x86_64/host-signal.h
> +++ b/linux-user/host/x86_64/host-signal.h
> @@ -1 +1,24 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef X86_64_HOST_SIGNAL_H
> +#define X86_64_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.gregs[REG_RIP];
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe
> + && (uc->uc_mcontext.gregs[REG_ERR] & 0x2);
> +}
> +
> +#endif
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 744af19397..474cb9cf82 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -29,19 +29,6 @@
> #include "trace/trace-root.h"
> #include "internal.h"
>
> -#undef EAX
> -#undef ECX
> -#undef EDX
> -#undef EBX
> -#undef ESP
> -#undef EBP
> -#undef ESI
> -#undef EDI
> -#undef EIP
> -#ifdef __linux__
> -#include <sys/ucontext.h>
> -#endif
> -
> __thread uintptr_t helper_retaddr;
>
> //#define DEBUG_SIGNAL
> @@ -268,123 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__i386__)
> -
> -#if defined(__NetBSD__)
> -#include <ucontext.h>
> -#include <machine/trap.h>
> -
> -#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
> -#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
> -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#elif defined(__FreeBSD__) || defined(__DragonFly__)
> -#include <ucontext.h>
> -#include <machine/trap.h>
> -
> -#define EIP_sig(context) (*((unsigned long
> *)&(context)->uc_mcontext.mc_eip))
> -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
> -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#elif defined(__OpenBSD__)
> -#include <machine/trap.h>
> -#define EIP_sig(context) ((context)->sc_eip)
> -#define TRAP_sig(context) ((context)->sc_trapno)
> -#define ERROR_sig(context) ((context)->sc_err)
> -#define MASK_sig(context) ((context)->sc_mask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#else
> -#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
> -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
> -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP 0xe
> -#endif
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
> - ucontext_t *uc = puc;
> -#elif defined(__OpenBSD__)
> - struct sigcontext *uc = puc;
> -#else
> - ucontext_t *uc = puc;
> -#endif
> - unsigned long pc;
> - int trapno;
> -
> -#ifndef REG_EIP
> -/* for glibc 2.1 */
> -#define REG_EIP EIP
> -#define REG_ERR ERR
> -#define REG_TRAPNO TRAPNO
> -#endif
> - pc = EIP_sig(uc);
> - trapno = TRAP_sig(uc);
> - return handle_cpu_signal(pc, info,
> - trapno == PAGE_FAULT_TRAP ?
> - (ERROR_sig(uc) >> 1) & 1 : 0,
> - &MASK_sig(uc));
> -}
> -
> -#elif defined(__x86_64__)
> -
> -#ifdef __NetBSD__
> -#include <machine/trap.h>
> -#define PC_sig(context) _UC_MACHINE_PC(context)
> -#define TRAP_sig(context)
> ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
> -#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#elif defined(__OpenBSD__)
> -#include <machine/trap.h>
> -#define PC_sig(context) ((context)->sc_rip)
> -#define TRAP_sig(context) ((context)->sc_trapno)
> -#define ERROR_sig(context) ((context)->sc_err)
> -#define MASK_sig(context) ((context)->sc_mask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#elif defined(__FreeBSD__) || defined(__DragonFly__)
> -#include <ucontext.h>
> -#include <machine/trap.h>
> -
> -#define PC_sig(context) (*((unsigned long
> *)&(context)->uc_mcontext.mc_rip))
> -#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
> -#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP T_PAGEFLT
> -#else
> -#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
> -#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
> -#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
> -#define MASK_sig(context) ((context)->uc_sigmask)
> -#define PAGE_FAULT_TRAP 0xe
> -#endif
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> - unsigned long pc;
> -#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
> - ucontext_t *uc = puc;
> -#elif defined(__OpenBSD__)
> - struct sigcontext *uc = puc;
> -#else
> - ucontext_t *uc = puc;
> -#endif
> -
> - pc = PC_sig(uc);
> - return handle_cpu_signal(pc, info,
> - TRAP_sig(uc) == PAGE_FAULT_TRAP ?
> - (ERROR_sig(uc) >> 1) & 1 : 0,
> - &MASK_sig(uc));
> -}
> -
> -#elif defined(_ARCH_PPC)
> +#if defined(_ARCH_PPC)
>
> /***********************************************************************
> * signal context platform-specific definitions
> @@ -895,11 +766,6 @@ int cpu_signal_handler(int host_signum, void *pinfo,
>
> return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> }
> -
> -#else
> -
> -#error host CPU specific signal handler needed
> -
> #endif
>
> /* The softmmu versions of these helpers are in cputlb.c. */
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 10438 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 08/67] linux-user/host/ppc: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (6 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 07/67] linux-user/host/x86: Populate host_signal.h Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 4:09 ` [PATCH v5 09/67] linux-user/host/alpha: " Richard Henderson
` (58 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/ppc/host-signal.h | 25 ++++++++-
linux-user/host/ppc64/host-signal.h | 2 +-
accel/tcg/user-exec.c | 79 +----------------------------
3 files changed, 26 insertions(+), 80 deletions(-)
diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h
index f4b4d65031..e09756c691 100644
--- a/linux-user/host/ppc/host-signal.h
+++ b/linux-user/host/ppc/host-signal.h
@@ -1 +1,24 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_HOST_SIGNAL_H
+#define PPC_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.regs->nip;
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ return uc->uc_mcontext.regs->trap != 0x400
+ && (uc->uc_mcontext.regs->dsisr & 0x02000000);
+}
+
+#endif
diff --git a/linux-user/host/ppc64/host-signal.h b/linux-user/host/ppc64/host-signal.h
index f4b4d65031..a353c22a90 100644
--- a/linux-user/host/ppc64/host-signal.h
+++ b/linux-user/host/ppc64/host-signal.h
@@ -1 +1 @@
-#define HOST_SIGNAL_PLACEHOLDER
+#include "../ppc/host-signal.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 474cb9cf82..e0cc765069 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,84 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(_ARCH_PPC)
-
-/***********************************************************************
- * signal context platform-specific definitions
- * From Wine
- */
-#ifdef linux
-/* All Registers access - only for local access */
-#define REG_sig(reg_name, context) \
- ((context)->uc_mcontext.regs->reg_name)
-/* Gpr Registers access */
-#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
-/* Program counter */
-#define IAR_sig(context) REG_sig(nip, context)
-/* Machine State Register (Supervisor) */
-#define MSR_sig(context) REG_sig(msr, context)
-/* Count register */
-#define CTR_sig(context) REG_sig(ctr, context)
-/* User's integer exception register */
-#define XER_sig(context) REG_sig(xer, context)
-/* Link register */
-#define LR_sig(context) REG_sig(link, context)
-/* Condition register */
-#define CR_sig(context) REG_sig(ccr, context)
-
-/* Float Registers access */
-#define FLOAT_sig(reg_num, context) \
- (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
-#define FPSCR_sig(context) \
- (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
-/* Exception Registers access */
-#define DAR_sig(context) REG_sig(dar, context)
-#define DSISR_sig(context) REG_sig(dsisr, context)
-#define TRAP_sig(context) REG_sig(trap, context)
-#endif /* linux */
-
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
-#include <ucontext.h>
-#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
-#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
-#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
-#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
-#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
-#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
-/* Exception Registers access */
-#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
-#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
-#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
-#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
- ucontext_t *uc = puc;
-#else
- ucontext_t *uc = puc;
-#endif
- unsigned long pc;
- int is_write;
-
- pc = IAR_sig(uc);
- is_write = 0;
-#if 0
- /* ppc 4xx case */
- if (DSISR_sig(uc) & 0x00800000) {
- is_write = 1;
- }
-#else
- if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
- is_write = 1;
- }
-#endif
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-
-#elif defined(__alpha__)
+#if defined(__alpha__)
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 09/67] linux-user/host/alpha: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (7 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 08/67] linux-user/host/ppc: " Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 4:09 ` [PATCH v5 10/67] linux-user/host/sparc: " Richard Henderson
` (57 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/alpha/host-signal.h | 41 +++++++++++++++++++++++++++++
accel/tcg/user-exec.c | 31 +---------------------
2 files changed, 42 insertions(+), 30 deletions(-)
create mode 100644 linux-user/host/alpha/host-signal.h
diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h
new file mode 100644
index 0000000000..e27704d832
--- /dev/null
+++ b/linux-user/host/alpha/host-signal.h
@@ -0,0 +1,41 @@
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ALPHA_HOST_SIGNAL_H
+#define ALPHA_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.sc_pc;
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ uint32_t *pc = (uint32_t *)host_signal_pc(uc);
+ uint32_t insn = *pc;
+
+ /* XXX: need kernel patch to get write flag faster */
+ switch (insn >> 26) {
+ case 0x0d: /* stw */
+ case 0x0e: /* stb */
+ case 0x0f: /* stq_u */
+ case 0x24: /* stf */
+ case 0x25: /* stg */
+ case 0x26: /* sts */
+ case 0x27: /* stt */
+ case 0x2c: /* stl */
+ case 0x2d: /* stq */
+ case 0x2e: /* stl_c */
+ case 0x2f: /* stq_c */
+ return true;
+ }
+ return false;
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e0cc765069..0db3c5cf3c 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,36 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__alpha__)
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- ucontext_t *uc = puc;
- uint32_t *pc = uc->uc_mcontext.sc_pc;
- uint32_t insn = *pc;
- int is_write = 0;
-
- /* XXX: need kernel patch to get write flag faster */
- switch (insn >> 26) {
- case 0x0d: /* stw */
- case 0x0e: /* stb */
- case 0x0f: /* stq_u */
- case 0x24: /* stf */
- case 0x25: /* stg */
- case 0x26: /* sts */
- case 0x27: /* stt */
- case 0x2c: /* stl */
- case 0x2d: /* stq */
- case 0x2e: /* stl_c */
- case 0x2f: /* stq_c */
- is_write = 1;
- }
-
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-#elif defined(__sparc__)
+#if defined(__sparc__)
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 10/67] linux-user/host/sparc: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (8 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 09/67] linux-user/host/alpha: " Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:30 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 11/67] linux-user/host/arm: " Richard Henderson
` (56 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Drop the Solaris code as completely unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++-
linux-user/host/sparc64/host-signal.h | 2 +-
accel/tcg/user-exec.c | 62 +--------------------------
3 files changed, 55 insertions(+), 63 deletions(-)
diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h
index f4b4d65031..232943a1db 100644
--- a/linux-user/host/sparc/host-signal.h
+++ b/linux-user/host/sparc/host-signal.h
@@ -1 +1,53 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SPARC_HOST_SIGNAL_H
+#define SPARC_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+#ifdef __arch64__
+ return uc->uc_mcontext.mc_gregs[MC_PC];
+#else
+ return uc->uc_mcontext.gregs[REG_PC];
+#endif
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ uint32_t insn = *(uint32_t *)host_signal_pc(uc);
+
+ if ((insn >> 30) == 3) {
+ switch ((insn >> 19) & 0x3f) {
+ case 0x05: /* stb */
+ case 0x15: /* stba */
+ case 0x06: /* sth */
+ case 0x16: /* stha */
+ case 0x04: /* st */
+ case 0x14: /* sta */
+ case 0x07: /* std */
+ case 0x17: /* stda */
+ case 0x0e: /* stx */
+ case 0x1e: /* stxa */
+ case 0x24: /* stf */
+ case 0x34: /* stfa */
+ case 0x27: /* stdf */
+ case 0x37: /* stdfa */
+ case 0x26: /* stqf */
+ case 0x36: /* stqfa */
+ case 0x25: /* stfsr */
+ case 0x3c: /* casa */
+ case 0x3e: /* casxa */
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/linux-user/host/sparc64/host-signal.h b/linux-user/host/sparc64/host-signal.h
index f4b4d65031..1191fe2d40 100644
--- a/linux-user/host/sparc64/host-signal.h
+++ b/linux-user/host/sparc64/host-signal.h
@@ -1 +1 @@
-#define HOST_SIGNAL_PLACEHOLDER
+#include "../sparc/host-signal.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 0db3c5cf3c..17fe867aeb 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__sparc__)
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- int is_write;
- uint32_t insn;
-#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
- uint32_t *regs = (uint32_t *)(info + 1);
- void *sigmask = (regs + 20);
- /* XXX: is there a standard glibc define ? */
- unsigned long pc = regs[1];
-#else
-#ifdef __linux__
- struct sigcontext *sc = puc;
- unsigned long pc = sc->sigc_regs.tpc;
- void *sigmask = (void *)sc->sigc_mask;
-#elif defined(__OpenBSD__)
- struct sigcontext *uc = puc;
- unsigned long pc = uc->sc_pc;
- void *sigmask = (void *)(long)uc->sc_mask;
-#elif defined(__NetBSD__)
- ucontext_t *uc = puc;
- unsigned long pc = _UC_MACHINE_PC(uc);
- void *sigmask = (void *)&uc->uc_sigmask;
-#endif
-#endif
-
- /* XXX: need kernel patch to get write flag faster */
- is_write = 0;
- insn = *(uint32_t *)pc;
- if ((insn >> 30) == 3) {
- switch ((insn >> 19) & 0x3f) {
- case 0x05: /* stb */
- case 0x15: /* stba */
- case 0x06: /* sth */
- case 0x16: /* stha */
- case 0x04: /* st */
- case 0x14: /* sta */
- case 0x07: /* std */
- case 0x17: /* stda */
- case 0x0e: /* stx */
- case 0x1e: /* stxa */
- case 0x24: /* stf */
- case 0x34: /* stfa */
- case 0x27: /* stdf */
- case 0x37: /* stdfa */
- case 0x26: /* stqf */
- case 0x36: /* stqfa */
- case 0x25: /* stfsr */
- case 0x3c: /* casa */
- case 0x3e: /* casxa */
- is_write = 1;
- break;
- }
- }
- return handle_cpu_signal(pc, info, is_write, sigmask);
-}
-
-#elif defined(__arm__)
+#if defined(__arm__)
#if defined(__NetBSD__)
#include <ucontext.h>
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 10/67] linux-user/host/sparc: Populate host_signal.h
2021-10-15 4:09 ` [PATCH v5 10/67] linux-user/host/sparc: " Richard Henderson
@ 2021-10-15 18:30 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 5212 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
> Drop the Solaris code as completely unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/sparc/host-signal.h | 54 ++++++++++++++++++++++-
> linux-user/host/sparc64/host-signal.h | 2 +-
> accel/tcg/user-exec.c | 62 +--------------------------
> 3 files changed, 55 insertions(+), 63 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
FreeBSD has dropped sparc64, but NetBSD/OpenBSD have not. There's
a number of issues with bsd-user on {Net,Open}BSD which this does
exacerbate,
but just noting it should suffice since those issues are much bigger deals.
Warner
> diff --git a/linux-user/host/sparc/host-signal.h
> b/linux-user/host/sparc/host-signal.h
> index f4b4d65031..232943a1db 100644
> --- a/linux-user/host/sparc/host-signal.h
> +++ b/linux-user/host/sparc/host-signal.h
> @@ -1 +1,53 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef SPARC_HOST_SIGNAL_H
> +#define SPARC_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> +#ifdef __arch64__
> + return uc->uc_mcontext.mc_gregs[MC_PC];
> +#else
> + return uc->uc_mcontext.gregs[REG_PC];
> +#endif
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + uint32_t insn = *(uint32_t *)host_signal_pc(uc);
> +
> + if ((insn >> 30) == 3) {
> + switch ((insn >> 19) & 0x3f) {
> + case 0x05: /* stb */
> + case 0x15: /* stba */
> + case 0x06: /* sth */
> + case 0x16: /* stha */
> + case 0x04: /* st */
> + case 0x14: /* sta */
> + case 0x07: /* std */
> + case 0x17: /* stda */
> + case 0x0e: /* stx */
> + case 0x1e: /* stxa */
> + case 0x24: /* stf */
> + case 0x34: /* stfa */
> + case 0x27: /* stdf */
> + case 0x37: /* stdfa */
> + case 0x26: /* stqf */
> + case 0x36: /* stqfa */
> + case 0x25: /* stfsr */
> + case 0x3c: /* casa */
> + case 0x3e: /* casxa */
> + return true;
> + }
> + }
> + return false;
> +}
> +
> +#endif
> diff --git a/linux-user/host/sparc64/host-signal.h
> b/linux-user/host/sparc64/host-signal.h
> index f4b4d65031..1191fe2d40 100644
> --- a/linux-user/host/sparc64/host-signal.h
> +++ b/linux-user/host/sparc64/host-signal.h
> @@ -1 +1 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +#include "../sparc/host-signal.h"
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 0db3c5cf3c..17fe867aeb 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -255,67 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__sparc__)
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> - int is_write;
> - uint32_t insn;
> -#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
> - uint32_t *regs = (uint32_t *)(info + 1);
> - void *sigmask = (regs + 20);
> - /* XXX: is there a standard glibc define ? */
> - unsigned long pc = regs[1];
> -#else
> -#ifdef __linux__
> - struct sigcontext *sc = puc;
> - unsigned long pc = sc->sigc_regs.tpc;
> - void *sigmask = (void *)sc->sigc_mask;
> -#elif defined(__OpenBSD__)
> - struct sigcontext *uc = puc;
> - unsigned long pc = uc->sc_pc;
> - void *sigmask = (void *)(long)uc->sc_mask;
> -#elif defined(__NetBSD__)
> - ucontext_t *uc = puc;
> - unsigned long pc = _UC_MACHINE_PC(uc);
> - void *sigmask = (void *)&uc->uc_sigmask;
> -#endif
> -#endif
> -
> - /* XXX: need kernel patch to get write flag faster */
> - is_write = 0;
> - insn = *(uint32_t *)pc;
> - if ((insn >> 30) == 3) {
> - switch ((insn >> 19) & 0x3f) {
> - case 0x05: /* stb */
> - case 0x15: /* stba */
> - case 0x06: /* sth */
> - case 0x16: /* stha */
> - case 0x04: /* st */
> - case 0x14: /* sta */
> - case 0x07: /* std */
> - case 0x17: /* stda */
> - case 0x0e: /* stx */
> - case 0x1e: /* stxa */
> - case 0x24: /* stf */
> - case 0x34: /* stfa */
> - case 0x27: /* stdf */
> - case 0x37: /* stdfa */
> - case 0x26: /* stqf */
> - case 0x36: /* stqfa */
> - case 0x25: /* stfsr */
> - case 0x3c: /* casa */
> - case 0x3e: /* casxa */
> - is_write = 1;
> - break;
> - }
> - }
> - return handle_cpu_signal(pc, info, is_write, sigmask);
> -}
> -
> -#elif defined(__arm__)
> +#if defined(__arm__)
>
> #if defined(__NetBSD__)
> #include <ucontext.h>
> --
> 2.25.1
>
>
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^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 11/67] linux-user/host/arm: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (9 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 10/67] linux-user/host/sparc: " Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:30 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 12/67] linux-user/host/aarch64: " Richard Henderson
` (55 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++-
accel/tcg/user-exec.c | 45 +------------------------------
2 files changed, 30 insertions(+), 45 deletions(-)
diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h
index f4b4d65031..6932224c1c 100644
--- a/linux-user/host/arm/host-signal.h
+++ b/linux-user/host/arm/host-signal.h
@@ -1 +1,29 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef ARM_HOST_SIGNAL_H
+#define ARM_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.arm_pc;
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ /*
+ * In the FSR, bit 11 is WnR, assuming a v6 or
+ * later processor. On v5 we will always report
+ * this as a read, which will fail later.
+ */
+ uint32_t fsr = uc->uc_mcontext.error_code;
+ return extract32(fsr, 11, 1);
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 17fe867aeb..5656c654e1 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__arm__)
-
-#if defined(__NetBSD__)
-#include <ucontext.h>
-#include <sys/siginfo.h>
-#endif
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
-#if defined(__NetBSD__)
- ucontext_t *uc = puc;
- siginfo_t *si = pinfo;
-#else
- ucontext_t *uc = puc;
-#endif
- unsigned long pc;
- uint32_t fsr;
- int is_write;
-
-#if defined(__NetBSD__)
- pc = uc->uc_mcontext.__gregs[_REG_R15];
-#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
- pc = uc->uc_mcontext.gregs[R15];
-#else
- pc = uc->uc_mcontext.arm_pc;
-#endif
-
-#ifdef __NetBSD__
- fsr = si->si_trap;
-#else
- fsr = uc->uc_mcontext.error_code;
-#endif
- /*
- * In the FSR, bit 11 is WnR, assuming a v6 or
- * later processor. On v5 we will always report
- * this as a read, which will fail later.
- */
- is_write = extract32(fsr, 11, 1);
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-
-#elif defined(__aarch64__)
+#if defined(__aarch64__)
#if defined(__NetBSD__)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 11/67] linux-user/host/arm: Populate host_signal.h
2021-10-15 4:09 ` [PATCH v5 11/67] linux-user/host/arm: " Richard Henderson
@ 2021-10-15 18:30 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:30 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 3325 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++-
> accel/tcg/user-exec.c | 45 +------------------------------
> 2 files changed, 30 insertions(+), 45 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/linux-user/host/arm/host-signal.h
> b/linux-user/host/arm/host-signal.h
> index f4b4d65031..6932224c1c 100644
> --- a/linux-user/host/arm/host-signal.h
> +++ b/linux-user/host/arm/host-signal.h
> @@ -1 +1,29 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef ARM_HOST_SIGNAL_H
> +#define ARM_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.arm_pc;
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + /*
> + * In the FSR, bit 11 is WnR, assuming a v6 or
> + * later processor. On v5 we will always report
> + * this as a read, which will fail later.
> + */
> + uint32_t fsr = uc->uc_mcontext.error_code;
> + return extract32(fsr, 11, 1);
> +}
> +
> +#endif
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 17fe867aeb..5656c654e1 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__arm__)
> -
> -#if defined(__NetBSD__)
> -#include <ucontext.h>
> -#include <sys/siginfo.h>
> -#endif
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> -#if defined(__NetBSD__)
> - ucontext_t *uc = puc;
> - siginfo_t *si = pinfo;
> -#else
> - ucontext_t *uc = puc;
> -#endif
> - unsigned long pc;
> - uint32_t fsr;
> - int is_write;
> -
> -#if defined(__NetBSD__)
> - pc = uc->uc_mcontext.__gregs[_REG_R15];
> -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 &&
> __GLIBC_MINOR__ <= 3))
> - pc = uc->uc_mcontext.gregs[R15];
> -#else
> - pc = uc->uc_mcontext.arm_pc;
> -#endif
> -
> -#ifdef __NetBSD__
> - fsr = si->si_trap;
> -#else
> - fsr = uc->uc_mcontext.error_code;
> -#endif
> - /*
> - * In the FSR, bit 11 is WnR, assuming a v6 or
> - * later processor. On v5 we will always report
> - * this as a read, which will fail later.
> - */
> - is_write = extract32(fsr, 11, 1);
> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> -}
> -
> -#elif defined(__aarch64__)
> +#if defined(__aarch64__)
>
> #if defined(__NetBSD__)
>
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 4374 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 12/67] linux-user/host/aarch64: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (10 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 11/67] linux-user/host/arm: " Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 18:30 ` Warner Losh
2021-10-15 4:09 ` [PATCH v5 13/67] linux-user/host/s390: " Richard Henderson
` (54 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Split host_signal_pc and host_signal_write out of user-exec.c.
Drop the *BSD code, to be re-created under bsd-user/ later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++-
accel/tcg/user-exec.c | 94 +--------------------------
2 files changed, 74 insertions(+), 94 deletions(-)
diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h
index f4b4d65031..02a55c3372 100644
--- a/linux-user/host/aarch64/host-signal.h
+++ b/linux-user/host/aarch64/host-signal.h
@@ -1 +1,73 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef AARCH64_HOST_SIGNAL_H
+#define AARCH64_HOST_SIGNAL_H
+
+/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
+#ifndef ESR_MAGIC
+#define ESR_MAGIC 0x45535201
+struct esr_context {
+ struct _aarch64_ctx head;
+ uint64_t esr;
+};
+#endif
+
+static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
+{
+ return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
+}
+
+static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
+{
+ return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
+}
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.pc;
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ struct _aarch64_ctx *hdr;
+ uint32_t insn;
+
+ /* Find the esr_context, which has the WnR bit in it */
+ for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
+ if (hdr->magic == ESR_MAGIC) {
+ struct esr_context const *ec = (struct esr_context const *)hdr;
+ uint64_t esr = ec->esr;
+
+ /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
+ return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
+ }
+ }
+
+ /*
+ * Fall back to parsing instructions; will only be needed
+ * for really ancient (pre-3.16) kernels.
+ */
+ insn = *(uint32_t *)host_signal_pc(uc);
+
+ return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
+ || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
+ || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
+ || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
+ || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
+ || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
+ || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
+ /* Ignore bits 10, 11 & 21, controlling indexing. */
+ || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
+ || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
+ /* Ignore bits 23 & 24, controlling indexing. */
+ || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5656c654e1..0915eb7f95 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__aarch64__)
-
-#if defined(__NetBSD__)
-
-#include <ucontext.h>
-#include <sys/siginfo.h>
-
-int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
-{
- ucontext_t *uc = puc;
- siginfo_t *si = pinfo;
- unsigned long pc;
- int is_write;
- uint32_t esr;
-
- pc = uc->uc_mcontext.__gregs[_REG_PC];
- esr = si->si_trap;
-
- /*
- * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
- * is 0b10010x: then bit 6 is the WnR bit
- */
- is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
- return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
-}
-
-#else
-
-#ifndef ESR_MAGIC
-/* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
-#define ESR_MAGIC 0x45535201
-struct esr_context {
- struct _aarch64_ctx head;
- uint64_t esr;
-};
-#endif
-
-static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
-{
- return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
-}
-
-static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
-{
- return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
-}
-
-int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
-{
- siginfo_t *info = pinfo;
- ucontext_t *uc = puc;
- uintptr_t pc = uc->uc_mcontext.pc;
- bool is_write;
- struct _aarch64_ctx *hdr;
- struct esr_context const *esrctx = NULL;
-
- /* Find the esr_context, which has the WnR bit in it */
- for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
- if (hdr->magic == ESR_MAGIC) {
- esrctx = (struct esr_context const *)hdr;
- break;
- }
- }
-
- if (esrctx) {
- /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
- uint64_t esr = esrctx->esr;
- is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
- } else {
- /*
- * Fall back to parsing instructions; will only be needed
- * for really ancient (pre-3.16) kernels.
- */
- uint32_t insn = *(uint32_t *)pc;
-
- is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
- || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
- || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
- || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
- || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
- || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
- || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
- /* Ignore bits 10, 11 & 21, controlling indexing. */
- || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
- || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
- /* Ignore bits 23 & 24, controlling indexing. */
- || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
- }
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-#endif
-
-#elif defined(__s390__)
+#if defined(__s390__)
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 12/67] linux-user/host/aarch64: Populate host_signal.h
2021-10-15 4:09 ` [PATCH v5 12/67] linux-user/host/aarch64: " Richard Henderson
@ 2021-10-15 18:30 ` Warner Losh
2021-10-15 19:49 ` Richard Henderson
0 siblings, 1 reply; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 7133 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
> Drop the *BSD code, to be re-created under bsd-user/ later.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/aarch64/host-signal.h | 74 ++++++++++++++++++++-
> accel/tcg/user-exec.c | 94 +--------------------------
> 2 files changed, 74 insertions(+), 94 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/linux-user/host/aarch64/host-signal.h
> b/linux-user/host/aarch64/host-signal.h
> index f4b4d65031..02a55c3372 100644
> --- a/linux-user/host/aarch64/host-signal.h
> +++ b/linux-user/host/aarch64/host-signal.h
> @@ -1 +1,73 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef AARCH64_HOST_SIGNAL_H
> +#define AARCH64_HOST_SIGNAL_H
> +
> +/* Pre-3.16 kernel headers don't have these, so provide fallback
> definitions */
> +#ifndef ESR_MAGIC
> +#define ESR_MAGIC 0x45535201
> +struct esr_context {
> + struct _aarch64_ctx head;
> + uint64_t esr;
> +};
> +#endif
> +
> +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
> +{
> + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
> +}
> +
> +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
> +{
> + return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
> +}
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.pc;
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + struct _aarch64_ctx *hdr;
> + uint32_t insn;
> +
> + /* Find the esr_context, which has the WnR bit in it */
> + for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
> + if (hdr->magic == ESR_MAGIC) {
> + struct esr_context const *ec = (struct esr_context const
> *)hdr;
> + uint64_t esr = ec->esr;
> +
> + /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR
> bit */
> + return extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1)
> == 1;
> + }
> + }
> +
> + /*
> + * Fall back to parsing instructions; will only be needed
> + * for really ancient (pre-3.16) kernels.
> + */
> + insn = *(uint32_t *)host_signal_pc(uc);
> +
> + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
> + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
> + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
> + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
> + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
> + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
> + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
> + /* Ignore bits 10, 11 & 21, controlling indexing. */
> + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
> + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
> + /* Ignore bits 23 & 24, controlling indexing. */
> + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */
> +}
> +
> +#endif
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 5656c654e1..0915eb7f95 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -255,99 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__aarch64__)
> -
> -#if defined(__NetBSD__)
> -
> -#include <ucontext.h>
> -#include <sys/siginfo.h>
> -
> -int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
> -{
> - ucontext_t *uc = puc;
> - siginfo_t *si = pinfo;
> - unsigned long pc;
> - int is_write;
> - uint32_t esr;
> -
> - pc = uc->uc_mcontext.__gregs[_REG_PC];
> - esr = si->si_trap;
> -
> - /*
> - * siginfo_t::si_trap is the ESR value, for data aborts ESR.EC
> - * is 0b10010x: then bit 6 is the WnR bit
> - */
> - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
> - return handle_cpu_signal(pc, si, is_write, &uc->uc_sigmask);
> -}
> -
> -#else
> -
> -#ifndef ESR_MAGIC
> -/* Pre-3.16 kernel headers don't have these, so provide fallback
> definitions */
> -#define ESR_MAGIC 0x45535201
> -struct esr_context {
> - struct _aarch64_ctx head;
> - uint64_t esr;
> -};
> -#endif
> -
> -static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
> -{
> - return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
> -}
> -
> -static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
> -{
> - return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
> -}
> -
> -int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
> -{
> - siginfo_t *info = pinfo;
> - ucontext_t *uc = puc;
> - uintptr_t pc = uc->uc_mcontext.pc;
> - bool is_write;
> - struct _aarch64_ctx *hdr;
> - struct esr_context const *esrctx = NULL;
> -
> - /* Find the esr_context, which has the WnR bit in it */
> - for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
> - if (hdr->magic == ESR_MAGIC) {
> - esrctx = (struct esr_context const *)hdr;
> - break;
> - }
> - }
> -
> - if (esrctx) {
> - /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit
> */
> - uint64_t esr = esrctx->esr;
> - is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1)
> == 1;
> - } else {
> - /*
> - * Fall back to parsing instructions; will only be needed
> - * for really ancient (pre-3.16) kernels.
> - */
> - uint32_t insn = *(uint32_t *)pc;
> -
> - is_write = ((insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
> - || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
> - || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
> - || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
> - || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
> - || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
> - || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit
> */
> - /* Ignore bits 10, 11 & 21, controlling indexing. */
> - || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
> - || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit
> */
> - /* Ignore bits 23 & 24, controlling indexing. */
> - || (insn & 0x3a400000) == 0x28000000); /*
> C3.3.7,14-16 */
> - }
> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> -}
> -#endif
> -
> -#elif defined(__s390__)
> +#if defined(__s390__)
>
> int cpu_signal_handler(int host_signum, void *pinfo,
> void *puc)
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 9143 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread* Re: [PATCH v5 12/67] linux-user/host/aarch64: Populate host_signal.h
2021-10-15 18:30 ` Warner Losh
@ 2021-10-15 19:49 ` Richard Henderson
0 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 19:49 UTC (permalink / raw)
To: Warner Losh; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
On 10/15/21 11:30 AM, Warner Losh wrote:
> + /*
> + * Fall back to parsing instructions; will only be needed
> + * for really ancient (pre-3.16) kernels.
> + */
> + insn = *(uint32_t *)host_signal_pc(uc);
> +
> + return (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
> + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
> + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
> + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
> + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
> + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
> + || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
> + /* Ignore bits 10, 11 & 21, controlling indexing. */
> + || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
> + || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
> + /* Ignore bits 23 & 24, controlling indexing. */
> + || (insn & 0x3a400000) == 0x28000000; /* C3.3.7,14-16 */
> +}
Oh, Warner, I was thinking about your query about sharing the instruction parsing code
between *-user.
I was thinking that we should have, under e.g. user-only/, a library of stuff that could
be referenced by *-user. One of these would be a simpler interface like
bool host_is_write_insn_at(void *pc);
We can hammer out details on that as you discover what you need in bsd-user.
r~
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 13/67] linux-user/host/s390: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (11 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 12/67] linux-user/host/aarch64: " Richard Henderson
@ 2021-10-15 4:09 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 14/67] linux-user/host/mips: " Richard Henderson
` (53 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:09 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/s390/host-signal.h | 93 ++++++++++++++++++++++++++++-
linux-user/host/s390x/host-signal.h | 2 +-
accel/tcg/user-exec.c | 88 +--------------------------
3 files changed, 94 insertions(+), 89 deletions(-)
diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h
index f4b4d65031..21f59b612a 100644
--- a/linux-user/host/s390/host-signal.h
+++ b/linux-user/host/s390/host-signal.h
@@ -1 +1,92 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef S390_HOST_SIGNAL_H
+#define S390_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.psw.addr;
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ uint16_t *pinsn = (uint16_t *)host_signal_pc(uc);
+
+ /*
+ * ??? On linux, the non-rt signal handler has 4 (!) arguments instead
+ * of the normal 2 arguments. The 4th argument contains the "Translation-
+ * Exception Identification for DAT Exceptions" from the hardware (aka
+ * "int_parm_long"), which does in fact contain the is_write value.
+ * The rt signal handler, as far as I can tell, does not give this value
+ * at all. Not that we could get to it from here even if it were.
+ * So fall back to parsing instructions. Treat read-modify-write ones as
+ * writes, which is not fully correct, but for tracking self-modifying code
+ * this is better than treating them as reads. Checking si_addr page flags
+ * might be a viable improvement, albeit a racy one.
+ */
+ /* ??? This is not even close to complete. */
+ switch (pinsn[0] >> 8) {
+ case 0x50: /* ST */
+ case 0x42: /* STC */
+ case 0x40: /* STH */
+ case 0xba: /* CS */
+ case 0xbb: /* CDS */
+ return true;
+ case 0xc4: /* RIL format insns */
+ switch (pinsn[0] & 0xf) {
+ case 0xf: /* STRL */
+ case 0xb: /* STGRL */
+ case 0x7: /* STHRL */
+ return true;
+ }
+ break;
+ case 0xc8: /* SSF format insns */
+ switch (pinsn[0] & 0xf) {
+ case 0x2: /* CSST */
+ return true;
+ }
+ break;
+ case 0xe3: /* RXY format insns */
+ switch (pinsn[2] & 0xff) {
+ case 0x50: /* STY */
+ case 0x24: /* STG */
+ case 0x72: /* STCY */
+ case 0x70: /* STHY */
+ case 0x8e: /* STPQ */
+ case 0x3f: /* STRVH */
+ case 0x3e: /* STRV */
+ case 0x2f: /* STRVG */
+ return true;
+ }
+ break;
+ case 0xeb: /* RSY format insns */
+ switch (pinsn[2] & 0xff) {
+ case 0x14: /* CSY */
+ case 0x30: /* CSG */
+ case 0x31: /* CDSY */
+ case 0x3e: /* CDSG */
+ case 0xe4: /* LANG */
+ case 0xe6: /* LAOG */
+ case 0xe7: /* LAXG */
+ case 0xe8: /* LAAG */
+ case 0xea: /* LAALG */
+ case 0xf4: /* LAN */
+ case 0xf6: /* LAO */
+ case 0xf7: /* LAX */
+ case 0xfa: /* LAAL */
+ case 0xf8: /* LAA */
+ return true;
+ }
+ break;
+ }
+ return false;
+}
+
+#endif
diff --git a/linux-user/host/s390x/host-signal.h b/linux-user/host/s390x/host-signal.h
index f4b4d65031..0e83f9358d 100644
--- a/linux-user/host/s390x/host-signal.h
+++ b/linux-user/host/s390x/host-signal.h
@@ -1 +1 @@
-#define HOST_SIGNAL_PLACEHOLDER
+#include "../s390/host-signal.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 0915eb7f95..bfd964b578 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,93 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__s390__)
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- ucontext_t *uc = puc;
- unsigned long pc;
- uint16_t *pinsn;
- int is_write = 0;
-
- pc = uc->uc_mcontext.psw.addr;
-
- /*
- * ??? On linux, the non-rt signal handler has 4 (!) arguments instead
- * of the normal 2 arguments. The 4th argument contains the "Translation-
- * Exception Identification for DAT Exceptions" from the hardware (aka
- * "int_parm_long"), which does in fact contain the is_write value.
- * The rt signal handler, as far as I can tell, does not give this value
- * at all. Not that we could get to it from here even if it were.
- * So fall back to parsing instructions. Treat read-modify-write ones as
- * writes, which is not fully correct, but for tracking self-modifying code
- * this is better than treating them as reads. Checking si_addr page flags
- * might be a viable improvement, albeit a racy one.
- */
- /* ??? This is not even close to complete. */
- pinsn = (uint16_t *)pc;
- switch (pinsn[0] >> 8) {
- case 0x50: /* ST */
- case 0x42: /* STC */
- case 0x40: /* STH */
- case 0xba: /* CS */
- case 0xbb: /* CDS */
- is_write = 1;
- break;
- case 0xc4: /* RIL format insns */
- switch (pinsn[0] & 0xf) {
- case 0xf: /* STRL */
- case 0xb: /* STGRL */
- case 0x7: /* STHRL */
- is_write = 1;
- }
- break;
- case 0xc8: /* SSF format insns */
- switch (pinsn[0] & 0xf) {
- case 0x2: /* CSST */
- is_write = 1;
- }
- break;
- case 0xe3: /* RXY format insns */
- switch (pinsn[2] & 0xff) {
- case 0x50: /* STY */
- case 0x24: /* STG */
- case 0x72: /* STCY */
- case 0x70: /* STHY */
- case 0x8e: /* STPQ */
- case 0x3f: /* STRVH */
- case 0x3e: /* STRV */
- case 0x2f: /* STRVG */
- is_write = 1;
- }
- break;
- case 0xeb: /* RSY format insns */
- switch (pinsn[2] & 0xff) {
- case 0x14: /* CSY */
- case 0x30: /* CSG */
- case 0x31: /* CDSY */
- case 0x3e: /* CDSG */
- case 0xe4: /* LANG */
- case 0xe6: /* LAOG */
- case 0xe7: /* LAXG */
- case 0xe8: /* LAAG */
- case 0xea: /* LAALG */
- case 0xf4: /* LAN */
- case 0xf6: /* LAO */
- case 0xf7: /* LAX */
- case 0xfa: /* LAAL */
- case 0xf8: /* LAA */
- is_write = 1;
- }
- break;
- }
-
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-
-#elif defined(__mips__)
+#if defined(__mips__)
#if defined(__misp16) || defined(__mips_micromips)
#error "Unsupported encoding"
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 14/67] linux-user/host/mips: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (12 preceding siblings ...)
2021-10-15 4:09 ` [PATCH v5 13/67] linux-user/host/s390: " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:31 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 15/67] linux-user/host/riscv: " Richard Henderson
` (52 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++-
accel/tcg/user-exec.c | 52 +------------------------
2 files changed, 62 insertions(+), 52 deletions(-)
diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h
index f4b4d65031..9c83e51130 100644
--- a/linux-user/host/mips/host-signal.h
+++ b/linux-user/host/mips/host-signal.h
@@ -1 +1,61 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef MIPS_HOST_SIGNAL_H
+#define MIPS_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.pc;
+}
+
+#if defined(__misp16) || defined(__mips_micromips)
+#error "Unsupported encoding"
+#endif
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ uint32_t insn = *(uint32_t *)host_signal_pc(uc);
+
+ /* Detect all store instructions at program counter. */
+ switch ((insn >> 26) & 077) {
+ case 050: /* SB */
+ case 051: /* SH */
+ case 052: /* SWL */
+ case 053: /* SW */
+ case 054: /* SDL */
+ case 055: /* SDR */
+ case 056: /* SWR */
+ case 070: /* SC */
+ case 071: /* SWC1 */
+ case 074: /* SCD */
+ case 075: /* SDC1 */
+ case 077: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+ case 072: /* SWC2 */
+ case 076: /* SDC2 */
+#endif
+ return true;
+ case 023: /* COP1X */
+ /*
+ * Required in all versions of MIPS64 since
+ * MIPS64r1 and subsequent versions of MIPS32r2.
+ */
+ switch (insn & 077) {
+ case 010: /* SWXC1 */
+ case 011: /* SDXC1 */
+ case 015: /* SUXC1 */
+ return true;
+ }
+ break;
+ }
+ return false;
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index bfd964b578..287f03dac5 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__mips__)
-
-#if defined(__misp16) || defined(__mips_micromips)
-#error "Unsupported encoding"
-#endif
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- ucontext_t *uc = puc;
- uintptr_t pc = uc->uc_mcontext.pc;
- uint32_t insn = *(uint32_t *)pc;
- int is_write = 0;
-
- /* Detect all store instructions at program counter. */
- switch((insn >> 26) & 077) {
- case 050: /* SB */
- case 051: /* SH */
- case 052: /* SWL */
- case 053: /* SW */
- case 054: /* SDL */
- case 055: /* SDR */
- case 056: /* SWR */
- case 070: /* SC */
- case 071: /* SWC1 */
- case 074: /* SCD */
- case 075: /* SDC1 */
- case 077: /* SD */
-#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
- case 072: /* SWC2 */
- case 076: /* SDC2 */
-#endif
- is_write = 1;
- break;
- case 023: /* COP1X */
- /* Required in all versions of MIPS64 since
- MIPS64r1 and subsequent versions of MIPS32r2. */
- switch (insn & 077) {
- case 010: /* SWXC1 */
- case 011: /* SDXC1 */
- case 015: /* SUXC1 */
- is_write = 1;
- }
- break;
- }
-
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-
-#elif defined(__riscv)
+#if defined(__riscv)
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 14/67] linux-user/host/mips: Populate host_signal.h
2021-10-15 4:10 ` [PATCH v5 14/67] linux-user/host/mips: " Richard Henderson
@ 2021-10-15 18:31 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:31 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 4500 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++-
> accel/tcg/user-exec.c | 52 +------------------------
> 2 files changed, 62 insertions(+), 52 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/linux-user/host/mips/host-signal.h
> b/linux-user/host/mips/host-signal.h
> index f4b4d65031..9c83e51130 100644
> --- a/linux-user/host/mips/host-signal.h
> +++ b/linux-user/host/mips/host-signal.h
> @@ -1 +1,61 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef MIPS_HOST_SIGNAL_H
> +#define MIPS_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.pc;
> +}
> +
> +#if defined(__misp16) || defined(__mips_micromips)
> +#error "Unsupported encoding"
> +#endif
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + uint32_t insn = *(uint32_t *)host_signal_pc(uc);
> +
> + /* Detect all store instructions at program counter. */
> + switch ((insn >> 26) & 077) {
> + case 050: /* SB */
> + case 051: /* SH */
> + case 052: /* SWL */
> + case 053: /* SW */
> + case 054: /* SDL */
> + case 055: /* SDR */
> + case 056: /* SWR */
> + case 070: /* SC */
> + case 071: /* SWC1 */
> + case 074: /* SCD */
> + case 075: /* SDC1 */
> + case 077: /* SD */
> +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
> + case 072: /* SWC2 */
> + case 076: /* SDC2 */
> +#endif
> + return true;
> + case 023: /* COP1X */
> + /*
> + * Required in all versions of MIPS64 since
> + * MIPS64r1 and subsequent versions of MIPS32r2.
> + */
> + switch (insn & 077) {
> + case 010: /* SWXC1 */
> + case 011: /* SDXC1 */
> + case 015: /* SUXC1 */
> + return true;
> + }
> + break;
> + }
> + return false;
> +}
> +
> +#endif
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index bfd964b578..287f03dac5 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__mips__)
> -
> -#if defined(__misp16) || defined(__mips_micromips)
> -#error "Unsupported encoding"
> -#endif
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> - ucontext_t *uc = puc;
> - uintptr_t pc = uc->uc_mcontext.pc;
> - uint32_t insn = *(uint32_t *)pc;
> - int is_write = 0;
> -
> - /* Detect all store instructions at program counter. */
> - switch((insn >> 26) & 077) {
> - case 050: /* SB */
> - case 051: /* SH */
> - case 052: /* SWL */
> - case 053: /* SW */
> - case 054: /* SDL */
> - case 055: /* SDR */
> - case 056: /* SWR */
> - case 070: /* SC */
> - case 071: /* SWC1 */
> - case 074: /* SCD */
> - case 075: /* SDC1 */
> - case 077: /* SD */
> -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
> - case 072: /* SWC2 */
> - case 076: /* SDC2 */
> -#endif
> - is_write = 1;
> - break;
> - case 023: /* COP1X */
> - /* Required in all versions of MIPS64 since
> - MIPS64r1 and subsequent versions of MIPS32r2. */
> - switch (insn & 077) {
> - case 010: /* SWXC1 */
> - case 011: /* SDXC1 */
> - case 015: /* SUXC1 */
> - is_write = 1;
> - }
> - break;
> - }
> -
> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> -}
> -
> -#elif defined(__riscv)
> +#if defined(__riscv)
>
> int cpu_signal_handler(int host_signum, void *pinfo,
> void *puc)
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 5771 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (13 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 14/67] linux-user/host/mips: " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:32 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
` (51 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, alex.bennee, laurent, imp
Split host_signal_pc and host_signal_write out of user-exec.c.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++-
accel/tcg/user-exec.c | 134 ----------------------------
2 files changed, 84 insertions(+), 135 deletions(-)
diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h
index f4b4d65031..5860dce7d7 100644
--- a/linux-user/host/riscv/host-signal.h
+++ b/linux-user/host/riscv/host-signal.h
@@ -1 +1,84 @@
-#define HOST_SIGNAL_PLACEHOLDER
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (C) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef RISCV_HOST_SIGNAL_H
+#define RISCV_HOST_SIGNAL_H
+
+static inline uintptr_t host_signal_pc(ucontext_t *uc)
+{
+ return uc->uc_mcontext.__gregs[REG_PC];
+}
+
+static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
+{
+ uint32_t insn = *(uint32_t *)host_signal_pc(uc);
+
+ /*
+ * Detect store by reading the instruction at the program
+ * counter. Note: we currently only generate 32-bit
+ * instructions so we thus only detect 32-bit stores
+ */
+ switch (((insn >> 0) & 0b11)) {
+ case 3:
+ switch (((insn >> 2) & 0b11111)) {
+ case 8:
+ switch (((insn >> 12) & 0b111)) {
+ case 0: /* sb */
+ case 1: /* sh */
+ case 2: /* sw */
+ case 3: /* sd */
+ case 4: /* sq */
+ return true;
+ default:
+ break;
+ }
+ break;
+ case 9:
+ switch (((insn >> 12) & 0b111)) {
+ case 2: /* fsw */
+ case 3: /* fsd */
+ case 4: /* fsq */
+ return true;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Check for compressed instructions */
+ switch (((insn >> 13) & 0b111)) {
+ case 7:
+ switch (insn & 0b11) {
+ case 0: /*c.sd */
+ case 2: /* c.sdsp */
+ return true;
+ default:
+ break;
+ }
+ break;
+ case 6:
+ switch (insn & 0b11) {
+ case 0: /* c.sw */
+ case 3: /* c.swsp */
+ return true;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return false;
+}
+
+#endif
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 287f03dac5..2d9ab0a8b8 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
}
}
-/*
- * 'pc' is the host PC at which the exception was raised.
- * 'address' is the effective address of the memory exception.
- * 'is_write' is 1 if a write caused the exception and otherwise 0.
- * 'old_set' is the signal set which should be restored.
- */
-static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
- int is_write, sigset_t *old_set)
-{
- CPUState *cpu = current_cpu;
- CPUClass *cc;
- unsigned long host_addr = (unsigned long)info->si_addr;
- MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
- abi_ptr guest_addr;
-
- /* For synchronous signals we expect to be coming from the vCPU
- * thread (so current_cpu should be valid) and either from running
- * code or during translation which can fault as we cross pages.
- *
- * If neither is true then something has gone wrong and we should
- * abort rather than try and restart the vCPU execution.
- */
- if (!cpu || !cpu->running) {
- printf("qemu:%s received signal outside vCPU context @ pc=0x%"
- PRIxPTR "\n", __func__, pc);
- abort();
- }
-
-#if defined(DEBUG_SIGNAL)
- printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
- pc, host_addr, is_write, *(unsigned long *)old_set);
-#endif
-
- /* Convert forcefully to guest address space, invalid addresses
- are still valid segv ones */
- guest_addr = h2g_nocheck(host_addr);
-
- /* XXX: locking issue */
- if (is_write &&
- info->si_signo == SIGSEGV &&
- info->si_code == SEGV_ACCERR &&
- h2g_valid(host_addr) &&
- handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
- return 1;
- }
-
- /*
- * There is no way the target can handle this other than raising
- * an exception. Undo signal and retaddr state prior to longjmp.
- */
- sigprocmask(SIG_SETMASK, old_set, NULL);
-
- cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
- MMU_USER_IDX, false, pc);
- g_assert_not_reached();
-}
-
static int probe_access_internal(CPUArchState *env, target_ulong addr,
int fault_size, MMUAccessType access_type,
bool nonfault, uintptr_t ra)
@@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
return size ? g2h(env_cpu(env), addr) : NULL;
}
-#if defined(__riscv)
-
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
-{
- siginfo_t *info = pinfo;
- ucontext_t *uc = puc;
- greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
- uint32_t insn = *(uint32_t *)pc;
- int is_write = 0;
-
- /* Detect store by reading the instruction at the program
- counter. Note: we currently only generate 32-bit
- instructions so we thus only detect 32-bit stores */
- switch (((insn >> 0) & 0b11)) {
- case 3:
- switch (((insn >> 2) & 0b11111)) {
- case 8:
- switch (((insn >> 12) & 0b111)) {
- case 0: /* sb */
- case 1: /* sh */
- case 2: /* sw */
- case 3: /* sd */
- case 4: /* sq */
- is_write = 1;
- break;
- default:
- break;
- }
- break;
- case 9:
- switch (((insn >> 12) & 0b111)) {
- case 2: /* fsw */
- case 3: /* fsd */
- case 4: /* fsq */
- is_write = 1;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
- }
-
- /* Check for compressed instructions */
- switch (((insn >> 13) & 0b111)) {
- case 7:
- switch (insn & 0b11) {
- case 0: /*c.sd */
- case 2: /* c.sdsp */
- is_write = 1;
- break;
- default:
- break;
- }
- break;
- case 6:
- switch (insn & 0b11) {
- case 0: /* c.sw */
- case 3: /* c.swsp */
- is_write = 1;
- break;
- default:
- break;
- }
- break;
- default:
- break;
- }
-
- return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
-}
-#endif
-
/* The softmmu versions of these helpers are in cputlb.c. */
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 15/67] linux-user/host/riscv: Populate host_signal.h
2021-10-15 4:10 ` [PATCH v5 15/67] linux-user/host/riscv: " Richard Henderson
@ 2021-10-15 18:32 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:32 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 8015 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c.
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/host/riscv/host-signal.h | 85 +++++++++++++++++-
> accel/tcg/user-exec.c | 134 ----------------------------
> 2 files changed, 84 insertions(+), 135 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/linux-user/host/riscv/host-signal.h
> b/linux-user/host/riscv/host-signal.h
> index f4b4d65031..5860dce7d7 100644
> --- a/linux-user/host/riscv/host-signal.h
> +++ b/linux-user/host/riscv/host-signal.h
> @@ -1 +1,84 @@
> -#define HOST_SIGNAL_PLACEHOLDER
> +/*
> + * host-signal.h: signal info dependent on the host architecture
> + *
> + * Copyright (C) 2021 Linaro Limited
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef RISCV_HOST_SIGNAL_H
> +#define RISCV_HOST_SIGNAL_H
> +
> +static inline uintptr_t host_signal_pc(ucontext_t *uc)
> +{
> + return uc->uc_mcontext.__gregs[REG_PC];
> +}
> +
> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
> +{
> + uint32_t insn = *(uint32_t *)host_signal_pc(uc);
> +
> + /*
> + * Detect store by reading the instruction at the program
> + * counter. Note: we currently only generate 32-bit
> + * instructions so we thus only detect 32-bit stores
> + */
> + switch (((insn >> 0) & 0b11)) {
> + case 3:
> + switch (((insn >> 2) & 0b11111)) {
> + case 8:
> + switch (((insn >> 12) & 0b111)) {
> + case 0: /* sb */
> + case 1: /* sh */
> + case 2: /* sw */
> + case 3: /* sd */
> + case 4: /* sq */
> + return true;
> + default:
> + break;
> + }
> + break;
> + case 9:
> + switch (((insn >> 12) & 0b111)) {
> + case 2: /* fsw */
> + case 3: /* fsd */
> + case 4: /* fsq */
> + return true;
> + default:
> + break;
> + }
> + break;
> + default:
> + break;
> + }
> + }
> +
> + /* Check for compressed instructions */
> + switch (((insn >> 13) & 0b111)) {
> + case 7:
> + switch (insn & 0b11) {
> + case 0: /*c.sd */
> + case 2: /* c.sdsp */
> + return true;
> + default:
> + break;
> + }
> + break;
> + case 6:
> + switch (insn & 0b11) {
> + case 0: /* c.sw */
> + case 3: /* c.swsp */
> + return true;
> + default:
> + break;
> + }
> + break;
> + default:
> + break;
> + }
> +
> + return false;
> +}
> +
> +#endif
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 287f03dac5..2d9ab0a8b8 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -139,64 +139,6 @@ bool handle_sigsegv_accerr_write(CPUState *cpu,
> sigset_t *old_set,
> }
> }
>
> -/*
> - * 'pc' is the host PC at which the exception was raised.
> - * 'address' is the effective address of the memory exception.
> - * 'is_write' is 1 if a write caused the exception and otherwise 0.
> - * 'old_set' is the signal set which should be restored.
> - */
> -static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
> - int is_write, sigset_t *old_set)
> -{
> - CPUState *cpu = current_cpu;
> - CPUClass *cc;
> - unsigned long host_addr = (unsigned long)info->si_addr;
> - MMUAccessType access_type = adjust_signal_pc(&pc, is_write);
> - abi_ptr guest_addr;
> -
> - /* For synchronous signals we expect to be coming from the vCPU
> - * thread (so current_cpu should be valid) and either from running
> - * code or during translation which can fault as we cross pages.
> - *
> - * If neither is true then something has gone wrong and we should
> - * abort rather than try and restart the vCPU execution.
> - */
> - if (!cpu || !cpu->running) {
> - printf("qemu:%s received signal outside vCPU context @ pc=0x%"
> - PRIxPTR "\n", __func__, pc);
> - abort();
> - }
> -
> -#if defined(DEBUG_SIGNAL)
> - printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
> - pc, host_addr, is_write, *(unsigned long *)old_set);
> -#endif
> -
> - /* Convert forcefully to guest address space, invalid addresses
> - are still valid segv ones */
> - guest_addr = h2g_nocheck(host_addr);
> -
> - /* XXX: locking issue */
> - if (is_write &&
> - info->si_signo == SIGSEGV &&
> - info->si_code == SEGV_ACCERR &&
> - h2g_valid(host_addr) &&
> - handle_sigsegv_accerr_write(cpu, old_set, pc, guest_addr)) {
> - return 1;
> - }
> -
> - /*
> - * There is no way the target can handle this other than raising
> - * an exception. Undo signal and retaddr state prior to longjmp.
> - */
> - sigprocmask(SIG_SETMASK, old_set, NULL);
> -
> - cc = CPU_GET_CLASS(cpu);
> - cc->tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
> - MMU_USER_IDX, false, pc);
> - g_assert_not_reached();
> -}
> -
> static int probe_access_internal(CPUArchState *env, target_ulong addr,
> int fault_size, MMUAccessType
> access_type,
> bool nonfault, uintptr_t ra)
> @@ -255,82 +197,6 @@ void *probe_access(CPUArchState *env, target_ulong
> addr, int size,
> return size ? g2h(env_cpu(env), addr) : NULL;
> }
>
> -#if defined(__riscv)
> -
> -int cpu_signal_handler(int host_signum, void *pinfo,
> - void *puc)
> -{
> - siginfo_t *info = pinfo;
> - ucontext_t *uc = puc;
> - greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
> - uint32_t insn = *(uint32_t *)pc;
> - int is_write = 0;
> -
> - /* Detect store by reading the instruction at the program
> - counter. Note: we currently only generate 32-bit
> - instructions so we thus only detect 32-bit stores */
> - switch (((insn >> 0) & 0b11)) {
> - case 3:
> - switch (((insn >> 2) & 0b11111)) {
> - case 8:
> - switch (((insn >> 12) & 0b111)) {
> - case 0: /* sb */
> - case 1: /* sh */
> - case 2: /* sw */
> - case 3: /* sd */
> - case 4: /* sq */
> - is_write = 1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case 9:
> - switch (((insn >> 12) & 0b111)) {
> - case 2: /* fsw */
> - case 3: /* fsd */
> - case 4: /* fsq */
> - is_write = 1;
> - break;
> - default:
> - break;
> - }
> - break;
> - default:
> - break;
> - }
> - }
> -
> - /* Check for compressed instructions */
> - switch (((insn >> 13) & 0b111)) {
> - case 7:
> - switch (insn & 0b11) {
> - case 0: /*c.sd */
> - case 2: /* c.sdsp */
> - is_write = 1;
> - break;
> - default:
> - break;
> - }
> - break;
> - case 6:
> - switch (insn & 0b11) {
> - case 0: /* c.sw */
> - case 3: /* c.swsp */
> - is_write = 1;
> - break;
> - default:
> - break;
> - }
> - break;
> - default:
> - break;
> - }
> -
> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
> -}
> -#endif
> -
> /* The softmmu versions of these helpers are in cputlb.c. */
>
> /*
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 10585 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (14 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 15/67] linux-user/host/riscv: " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:32 ` Warner Losh
2021-10-29 23:27 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write Richard Henderson
` (50 subsequent siblings)
66 siblings, 2 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
The named function no longer exists.
Refer to host_signal_handler instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index dab5f1d1cd..07be55b7e1 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64)
* linux-user/ in its get_user/put_user macros.
*
* TODO: Construct some helpers, written in assembly, that interact with
- * handle_cpu_signal to produce memory ops which can properly report errors
+ * host_signal_handler to produce memory ops which can properly report errors
* without racing.
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal
2021-10-15 4:10 ` [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
@ 2021-10-15 18:32 ` Warner Losh
2021-10-29 23:27 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 934 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> The named function no longer exists.
> Refer to host_signal_handler instead.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index dab5f1d1cd..07be55b7e1 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64)
> * linux-user/ in its get_user/put_user macros.
> *
> * TODO: Construct some helpers, written in assembly, that interact with
> - * handle_cpu_signal to produce memory ops which can properly report
> errors
> + * host_signal_handler to produce memory ops which can properly report
> errors
> * without racing.
> */
>
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 1614 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* Re: [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal
2021-10-15 4:10 ` [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
2021-10-15 18:32 ` Warner Losh
@ 2021-10-29 23:27 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> The named function no longer exists.
It seems to be declared inlined since QEMU v0.1.0 in 2003!
So it was likely a typo.
Anyhow,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Refer to host_signal_handler instead.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/sve_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index dab5f1d1cd..07be55b7e1 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -6118,7 +6118,7 @@ DO_LDN_2(4, dd, MO_64)
> * linux-user/ in its get_user/put_user macros.
> *
> * TODO: Construct some helpers, written in assembly, that interact with
> - * handle_cpu_signal to produce memory ops which can properly report errors
> + * host_signal_handler to produce memory ops which can properly report errors
> * without racing.
> */
>
>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (15 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 16/67] target/arm: Fixup comment re handle_cpu_signal Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
` (49 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, alex.bennee, laurent, imp
Do not read 4 bytes before we determine the size of the insn.
Simplify triple switches in favor of checking major opcodes.
Include the missing cases of compact fsd and fsdsp.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/host/riscv/host-signal.h | 83 ++++++++++-------------------
1 file changed, 28 insertions(+), 55 deletions(-)
diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h
index 5860dce7d7..ab06d70964 100644
--- a/linux-user/host/riscv/host-signal.h
+++ b/linux-user/host/riscv/host-signal.h
@@ -17,65 +17,38 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc)
static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)
{
- uint32_t insn = *(uint32_t *)host_signal_pc(uc);
-
/*
- * Detect store by reading the instruction at the program
- * counter. Note: we currently only generate 32-bit
- * instructions so we thus only detect 32-bit stores
+ * Detect store by reading the instruction at the program counter.
+ * Do not read more than 16 bits, because we have not yet determined
+ * the size of the instruction.
*/
- switch (((insn >> 0) & 0b11)) {
- case 3:
- switch (((insn >> 2) & 0b11111)) {
- case 8:
- switch (((insn >> 12) & 0b111)) {
- case 0: /* sb */
- case 1: /* sh */
- case 2: /* sw */
- case 3: /* sd */
- case 4: /* sq */
- return true;
- default:
- break;
- }
- break;
- case 9:
- switch (((insn >> 12) & 0b111)) {
- case 2: /* fsw */
- case 3: /* fsd */
- case 4: /* fsq */
- return true;
- default:
- break;
- }
- break;
- default:
- break;
- }
+ const uint16_t *pinsn = (const uint16_t *)host_signal_pc(uc);
+ uint16_t insn = pinsn[0];
+
+ /* 16-bit instructions */
+ switch (insn & 0xe003) {
+ case 0xa000: /* c.fsd */
+ case 0xc000: /* c.sw */
+ case 0xe000: /* c.sd (rv64) / c.fsw (rv32) */
+ case 0xa002: /* c.fsdsp */
+ case 0xc002: /* c.swsp */
+ case 0xe002: /* c.sdsp (rv64) / c.fswsp (rv32) */
+ return true;
}
- /* Check for compressed instructions */
- switch (((insn >> 13) & 0b111)) {
- case 7:
- switch (insn & 0b11) {
- case 0: /*c.sd */
- case 2: /* c.sdsp */
- return true;
- default:
- break;
- }
- break;
- case 6:
- switch (insn & 0b11) {
- case 0: /* c.sw */
- case 3: /* c.swsp */
- return true;
- default:
- break;
- }
- break;
- default:
- break;
+ /* 32-bit instructions, major opcodes */
+ switch (insn & 0x7f) {
+ case 0x23: /* store */
+ case 0x27: /* store-fp */
+ return true;
+ case 0x2f: /* amo */
+ /*
+ * The AMO function code is in bits 25-31, unread as yet.
+ * The AMO functions are LR (read), SC (write), and the
+ * rest are all read-modify-write.
+ */
+ insn = pinsn[1];
+ return (insn >> 11) != 2; /* LR */
}
return false;
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (16 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 17/67] linux-user/host/riscv: Improve host_signal_write Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
` (48 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Now that all of the linux-user hosts have been converted
to host-signal.h, drop the compatibility code.
Reviewed by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 12 ------------
linux-user/signal.c | 14 --------------
2 files changed, 26 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5f94d799aa..5dd663c153 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -685,18 +685,6 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
uintptr_t host_pc, abi_ptr guest_addr);
-/**
- * cpu_signal_handler
- * @signum: host signal number
- * @pinfo: host siginfo_t
- * @puc: host ucontext_t
- *
- * To be called from the SIGBUS and SIGSEGV signal handler to inform the
- * virtual cpu of exceptions. Returns true if the signal was handled by
- * the virtual CPU.
- */
-int cpu_signal_handler(int signum, void *pinfo, void *puc);
-
#else
static inline void mmap_lock(void) {}
static inline void mmap_unlock(void) {}
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 6900acb122..b816678ba5 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -780,17 +780,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
ucontext_t *uc = puc;
struct emulated_sigtable *k;
int guest_sig;
-
-#ifdef HOST_SIGNAL_PLACEHOLDER
- /* the CPU emulator uses some host signals to detect exceptions,
- we forward to it some signals */
- if ((host_sig == SIGSEGV || host_sig == SIGBUS)
- && info->si_code > 0) {
- if (cpu_signal_handler(host_sig, info, puc)) {
- return;
- }
- }
-#else
uintptr_t pc = 0;
bool sync_sig = false;
@@ -850,7 +839,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
sync_sig = true;
}
-#endif
/* get target signal number */
guest_sig = host_to_target_signal(host_sig);
@@ -865,7 +853,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
k->pending = guest_sig;
ts->signal_pending = 1;
-#ifndef HOST_SIGNAL_PLACEHOLDER
/*
* For synchronous signals, unwind the cpu state to the faulting
* insn and then exit back to the main loop so that the signal
@@ -875,7 +862,6 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
cpu->exception_index = EXCP_INTERRUPT;
cpu_loop_exit_restore(cpu, pc);
}
-#endif
rewind_if_in_safe_syscall(puc);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (17 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 18/67] linux-user/signal: Drop HOST_SIGNAL_PLACEHOLDER Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
` (47 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Add a new user-only interface for updating cpu state before
raising a signal. This will replace tlb_fill for user-only
and should result in less boilerplate for each guest.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 6cbe17f2e6..41718b695b 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -111,6 +111,32 @@ struct TCGCPUOps {
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
+#else
+ /**
+ * record_sigsegv:
+ * @cpu: cpu context
+ * @addr: faulting guest address
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGSEGV with si_code set for @maperr,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide anything to the signal
+ * handler with anything besides the user context registers, and
+ * the siginfo_t, then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided
+ * so that a "normal" cpu exception can be raised. In this case,
+ * the signal must be raised by the architecture cpu_loop.
+ */
+ void (*record_sigsegv)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (18 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 19/67] hw/core: Add TCGCPUOps.record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
` (46 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
This is a new interface to be provided by the os emulator for
raising SIGSEGV on fault. Use the new record_sigsegv target hook.
Reviewed by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 15 +++++++++++++++
accel/tcg/user-exec.c | 33 ++++++++++++++++++---------------
linux-user/signal.c | 30 ++++++++++++++++++++++--------
3 files changed, 55 insertions(+), 23 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 5dd663c153..f74578500c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -685,6 +685,21 @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write);
bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set,
uintptr_t host_pc, abi_ptr guest_addr);
+/**
+ * cpu_loop_exit_sigsegv:
+ * @cpu: the cpu context
+ * @addr: the guest address of the fault
+ * @access_type: access was read/write/execute
+ * @maperr: true for invalid page, false for permission fault
+ * @ra: host pc for unwinding
+ *
+ * Use the TCGCPUOps hook to record cpu state, do guest operating system
+ * specific things to raise SIGSEGV, and jump to the main cpu loop.
+ */
+void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+
#else
static inline void mmap_lock(void) {}
static inline void mmap_unlock(void) {}
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 2d9ab0a8b8..5646f8e527 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -143,35 +143,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
int fault_size, MMUAccessType access_type,
bool nonfault, uintptr_t ra)
{
- int flags;
+ int acc_flag;
+ bool maperr;
switch (access_type) {
case MMU_DATA_STORE:
- flags = PAGE_WRITE;
+ acc_flag = PAGE_WRITE_ORG;
break;
case MMU_DATA_LOAD:
- flags = PAGE_READ;
+ acc_flag = PAGE_READ;
break;
case MMU_INST_FETCH:
- flags = PAGE_EXEC;
+ acc_flag = PAGE_EXEC;
break;
default:
g_assert_not_reached();
}
- if (!guest_addr_valid_untagged(addr) ||
- page_check_range(addr, 1, flags) < 0) {
- if (nonfault) {
- return TLB_INVALID_MASK;
- } else {
- CPUState *cpu = env_cpu(env);
- CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
- g_assert_not_reached();
+ if (guest_addr_valid_untagged(addr)) {
+ int page_flags = page_get_flags(addr);
+ if (page_flags & acc_flag) {
+ return 0; /* success */
}
+ maperr = !(page_flags & PAGE_VALID);
+ } else {
+ maperr = true;
}
- return 0;
+
+ if (nonfault) {
+ return TLB_INVALID_MASK;
+ }
+
+ cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra);
}
int probe_access_flags(CPUArchState *env, target_ulong addr,
diff --git a/linux-user/signal.c b/linux-user/signal.c
index b816678ba5..135983747d 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -688,9 +688,27 @@ void force_sigsegv(int oldsig)
}
force_sig(TARGET_SIGSEGV);
}
-
#endif
+void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type, bool maperr, uintptr_t ra)
+{
+ const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+
+ if (tcg_ops->record_sigsegv) {
+ tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
+ } else if (tcg_ops->tlb_fill) {
+ tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra);
+ g_assert_not_reached();
+ }
+
+ force_sig_fault(TARGET_SIGSEGV,
+ maperr ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR,
+ addr);
+ cpu->exception_index = EXCP_INTERRUPT;
+ cpu_loop_exit_restore(cpu, ra);
+}
+
/* abort execution with signal */
static void QEMU_NORETURN dump_core_and_abort(int target_sig)
{
@@ -806,7 +824,7 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
access_type = adjust_signal_pc(&pc, is_write);
if (host_sig == SIGSEGV) {
- const struct TCGCPUOps *tcg_ops;
+ bool maperr = true;
if (info->si_code == SEGV_ACCERR && h2g_valid(host_addr)) {
/* If this was a write to a TB protected page, restart. */
@@ -821,18 +839,14 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
* which means that we may get ACCERR when we want MAPERR.
*/
if (page_get_flags(guest_addr) & PAGE_VALID) {
- /* maperr = false; */
+ maperr = false;
} else {
info->si_code = SEGV_MAPERR;
}
}
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
-
- tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
- tcg_ops->tlb_fill(cpu, guest_addr, 0, access_type,
- MMU_USER_IDX, false, pc);
- g_assert_not_reached();
+ cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
} else {
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (19 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 20/67] linux-user: Add cpu_loop_exit_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
` (45 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Record trap_arg{0,1,2} for the linux-user signal frame.
Fill in the stores to trap_arg{1,2} that were missing
from the previous user-only alpha_cpu_tlb_fill function.
Use maperr to simplify computation of trap_arg1.
Remove the code for EXCP_MMFAULT from cpu_loop, as
that part is now handled by cpu_loop_exit_sigsegv.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 13 +++++++++----
linux-user/alpha/cpu_loop.c | 8 --------
target/alpha/cpu.c | 6 ++++--
target/alpha/helper.c | 39 ++++++++++++++++++++++++++++++++-----
4 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 772828cc26..d49cc36d07 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -439,9 +439,6 @@ void alpha_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU
void alpha_cpu_list(void);
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
@@ -449,7 +446,15 @@ uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
uint64_t cpu_alpha_load_gr(CPUAlphaState *env, unsigned reg);
void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
-#ifndef CONFIG_USER_ONLY
+
+#ifdef CONFIG_USER_ONLY
+void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr);
+#else
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c
index 1b00a81385..4cc8e0a55c 100644
--- a/linux-user/alpha/cpu_loop.c
+++ b/linux-user/alpha/cpu_loop.c
@@ -54,14 +54,6 @@ void cpu_loop(CPUAlphaState *env)
fprintf(stderr, "External interrupt. Exit\n");
exit(EXIT_FAILURE);
break;
- case EXCP_MMFAULT:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
- ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
- info._sifields._sigfault._addr = env->trap_arg0;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_UNALIGN:
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 93e16a2ffb..69f32c3078 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,9 +218,11 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
- .tlb_fill = alpha_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = alpha_cpu_record_sigsegv,
+#else
+ .tlb_fill = alpha_cpu_tlb_fill,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 81550d9e2f..b7e7f73b15 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -120,15 +120,44 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
}
#if defined(CONFIG_USER_ONLY)
-bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
+ target_ulong mmcsr, cause;
- cs->exception_index = EXCP_MMFAULT;
+ /* Assuming !maperr, infer the missing protection. */
+ switch (access_type) {
+ case MMU_DATA_LOAD:
+ mmcsr = MM_K_FOR;
+ cause = 0;
+ break;
+ case MMU_DATA_STORE:
+ mmcsr = MM_K_FOW;
+ cause = 1;
+ break;
+ case MMU_INST_FETCH:
+ mmcsr = MM_K_FOE;
+ cause = -1;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ if (maperr) {
+ if (address < BIT_ULL(TARGET_VIRT_ADDR_SPACE_BITS - 1)) {
+ /* Userspace address, therefore page not mapped. */
+ mmcsr = MM_K_TNV;
+ } else {
+ /* Kernel or invalid address. */
+ mmcsr = MM_K_ACV;
+ }
+ }
+
+ /* Record the arguments that PALcode would give to the kernel. */
cpu->env.trap_arg0 = address;
- cpu_loop_exit_restore(cs, retaddr);
+ cpu->env.trap_arg1 = mmcsr;
+ cpu->env.trap_arg2 = cause;
}
#else
/* Returns the OSF/1 entMM failure indication, or -1 on success. */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (20 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 21/67] target/alpha: Implement alpha_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:34 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
` (44 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Use the new os interface for raising the exception,
rather than calling arm_cpu_tlb_fill directly.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mte_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 724175210b..e09b7e46a2 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
uintptr_t index;
if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
- /* SIGSEGV */
- arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
- ptr_mmu_idx, false, ra);
- g_assert_not_reached();
+ cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access,
+ !(flags & PAGE_VALID), ra);
}
/* Require both MAP_ANON and PROT_MTE for the page. */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup
2021-10-15 4:10 ` [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
@ 2021-10-15 18:34 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:34 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 1271 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Use the new os interface for raising the exception,
> rather than calling arm_cpu_tlb_fill directly.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/mte_helper.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
> index 724175210b..e09b7e46a2 100644
> --- a/target/arm/mte_helper.c
> +++ b/target/arm/mte_helper.c
> @@ -84,10 +84,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env,
> int ptr_mmu_idx,
> uintptr_t index;
>
> if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG :
> PAGE_READ))) {
> - /* SIGSEGV */
> - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
> - ptr_mmu_idx, false, ra);
> - g_assert_not_reached();
> + cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access,
> + !(flags & PAGE_VALID), ra);
> }
>
> /* Require both MAP_ANON and PROT_MTE for the page. */
> --
> 2.25.1
>
>
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^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (21 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 22/67] target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:35 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
` (43 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Because of the complexity of setting ESR, continue to use
arm_deliver_fault. This means we cannot remove the code
within cpu_loop that decodes EXCP_DATA_ABORT and
EXCP_PREFETCH_ABORT.
But using the new hook means that we don't have to do the
page_get_flags check manually, and we'll be able to restrict
the tlb_fill hook to sysemu later.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 6 ++++++
target/arm/cpu.c | 6 ++++--
target/arm/cpu_tcg.c | 6 ++++--
target/arm/tlb_helper.c | 36 +++++++++++++++++++-----------------
4 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3612107ab2..5a7aaf0f51 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult result)
return result != MEMTX_DECODE_ERROR;
}
+#ifdef CONFIG_USER_ONLY
+void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#endif
static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
{
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 641a8c2d3d..7a18a58ca0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
static const struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
-#if !defined(CONFIG_USER_ONLY)
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = arm_cpu_record_sigsegv,
+#else
+ .tlb_fill = arm_cpu_tlb_fill,
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
.do_interrupt = arm_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0d5adccf1a..7b3bea2fbb 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj)
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
-#if !defined(CONFIG_USER_ONLY)
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = arm_cpu_record_sigsegv,
+#else
+ .tlb_fill = arm_cpu_tlb_fill,
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
.do_interrupt = arm_v7m_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 3107f9823e..dc5860180f 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
}
-#endif /* !defined(CONFIG_USER_ONLY) */
-
bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
ARMCPU *cpu = ARM_CPU(cs);
ARMMMUFaultInfo fi = {};
-
-#ifdef CONFIG_USER_ONLY
- int flags = page_get_flags(useronly_clean_ptr(address));
- if (flags & PAGE_VALID) {
- fi.type = ARMFault_Permission;
- } else {
- fi.type = ARMFault_Translation;
- }
- fi.level = 3;
-
- /* now we have a real cpu fault */
- cpu_restore_state(cs, retaddr, true);
- arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
-#else
hwaddr phys_addr;
target_ulong page_size;
int prot, ret;
@@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_restore_state(cs, retaddr, true);
arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
}
-#endif
}
+#else
+void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra)
+{
+ ARMMMUFaultInfo fi = {
+ .type = maperr ? ARMFault_Translation : ARMFault_Permission,
+ .level = 3,
+ };
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ /*
+ * We report both ESR and FAR to signal handlers.
+ * For now, it's easiest to deliver the fault normally.
+ */
+ cpu_restore_state(cs, ra, true);
+ arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
+}
+#endif /* !defined(CONFIG_USER_ONLY) */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv
2021-10-15 4:10 ` [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 18:35 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:35 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 5186 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Because of the complexity of setting ESR, continue to use
> arm_deliver_fault. This means we cannot remove the code
> within cpu_loop that decodes EXCP_DATA_ABORT and
> EXCP_PREFETCH_ABORT.
>
> But using the new hook means that we don't have to do the
> page_get_flags check manually, and we'll be able to restrict
> the tlb_fill hook to sysemu later.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/internals.h | 6 ++++++
> target/arm/cpu.c | 6 ++++--
> target/arm/cpu_tcg.c | 6 ++++--
> target/arm/tlb_helper.c | 36 +++++++++++++++++++-----------------
> 4 files changed, 33 insertions(+), 21 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 3612107ab2..5a7aaf0f51 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -544,9 +544,15 @@ static inline bool arm_extabort_type(MemTxResult
> result)
> return result != MEMTX_DECODE_ERROR;
> }
>
> +#ifdef CONFIG_USER_ONLY
> +void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type,
> + bool maperr, uintptr_t ra);
> +#else
> bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> +#endif
>
> static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
> {
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 641a8c2d3d..7a18a58ca0 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2031,10 +2031,12 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
> static const struct TCGCPUOps arm_tcg_ops = {
> .initialize = arm_translate_init,
> .synchronize_from_tb = arm_cpu_synchronize_from_tb,
> - .tlb_fill = arm_cpu_tlb_fill,
> .debug_excp_handler = arm_debug_excp_handler,
>
> -#if !defined(CONFIG_USER_ONLY)
> +#ifdef CONFIG_USER_ONLY
> + .record_sigsegv = arm_cpu_record_sigsegv,
> +#else
> + .tlb_fill = arm_cpu_tlb_fill,
> .cpu_exec_interrupt = arm_cpu_exec_interrupt,
> .do_interrupt = arm_cpu_do_interrupt,
> .do_transaction_failed = arm_cpu_do_transaction_failed,
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 0d5adccf1a..7b3bea2fbb 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -898,10 +898,12 @@ static void pxa270c5_initfn(Object *obj)
> static const struct TCGCPUOps arm_v7m_tcg_ops = {
> .initialize = arm_translate_init,
> .synchronize_from_tb = arm_cpu_synchronize_from_tb,
> - .tlb_fill = arm_cpu_tlb_fill,
> .debug_excp_handler = arm_debug_excp_handler,
>
> -#if !defined(CONFIG_USER_ONLY)
> +#ifdef CONFIG_USER_ONLY
> + .record_sigsegv = arm_cpu_record_sigsegv,
> +#else
> + .tlb_fill = arm_cpu_tlb_fill,
> .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
> .do_interrupt = arm_v7m_cpu_do_interrupt,
> .do_transaction_failed = arm_cpu_do_transaction_failed,
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index 3107f9823e..dc5860180f 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -147,28 +147,12 @@ void arm_cpu_do_transaction_failed(CPUState *cs,
> hwaddr physaddr,
> arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
> }
>
> -#endif /* !defined(CONFIG_USER_ONLY) */
> -
> bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr)
> {
> ARMCPU *cpu = ARM_CPU(cs);
> ARMMMUFaultInfo fi = {};
> -
> -#ifdef CONFIG_USER_ONLY
> - int flags = page_get_flags(useronly_clean_ptr(address));
> - if (flags & PAGE_VALID) {
> - fi.type = ARMFault_Permission;
> - } else {
> - fi.type = ARMFault_Translation;
> - }
> - fi.level = 3;
> -
> - /* now we have a real cpu fault */
> - cpu_restore_state(cs, retaddr, true);
> - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
> -#else
> hwaddr phys_addr;
> target_ulong page_size;
> int prot, ret;
> @@ -210,5 +194,23 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> cpu_restore_state(cs, retaddr, true);
> arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
> }
> -#endif
> }
> +#else
> +void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
> + MMUAccessType access_type,
> + bool maperr, uintptr_t ra)
> +{
> + ARMMMUFaultInfo fi = {
> + .type = maperr ? ARMFault_Translation : ARMFault_Permission,
> + .level = 3,
> + };
> + ARMCPU *cpu = ARM_CPU(cs);
> +
> + /*
> + * We report both ESR and FAR to signal handlers.
> + * For now, it's easiest to deliver the fault normally.
> + */
> + cpu_restore_state(cs, ra, true);
> + arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
> +}
> +#endif /* !defined(CONFIG_USER_ONLY) */
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 6538 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (22 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 23/67] target/arm: Implement arm_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
` (42 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for cris linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
This makes all of the code in helper.c sysemu only, so remove the
ifdefs and move the file to cris_softmmu_ss.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/cpu.h | 8 ++++----
linux-user/cris/cpu_loop.c | 10 ----------
target/cris/cpu.c | 4 ++--
target/cris/helper.c | 18 ------------------
target/cris/meson.build | 7 +++++--
5 files changed, 11 insertions(+), 36 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 6603565f83..b445b194ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -189,6 +189,10 @@ extern const VMStateDescription vmstate_cris_cpu;
void cris_cpu_do_interrupt(CPUState *cpu);
void crisv10_cpu_do_interrupt(CPUState *cpu);
bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
+bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
#endif
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
@@ -251,10 +255,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
return !!(env->pregs[PR_CCS] & U_FLAG);
}
-bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
-
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c
index b9085619c4..0d5d268609 100644
--- a/linux-user/cris/cpu_loop.c
+++ b/linux-user/cris/cpu_loop.c
@@ -37,16 +37,6 @@ void cpu_loop(CPUCRISState *env)
process_queued_cpu_work(cs);
switch (trapnr) {
- case 0xaa:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->pregs[PR_EDA];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index c2e7483f5b..ed6c781342 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -205,9 +205,9 @@ static const struct SysemuCPUOps cris_sysemu_ops = {
static const struct TCGCPUOps crisv10_tcg_ops = {
.initialize = cris_initialize_crisv10_tcg,
- .tlb_fill = cris_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = cris_cpu_tlb_fill,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.do_interrupt = crisv10_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
@@ -215,9 +215,9 @@ static const struct TCGCPUOps crisv10_tcg_ops = {
static const struct TCGCPUOps crisv32_tcg_ops = {
.initialize = cris_initialize_tcg,
- .tlb_fill = cris_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = cris_cpu_tlb_fill,
.cpu_exec_interrupt = cris_cpu_exec_interrupt,
.do_interrupt = cris_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 36926faf32..a0d6ecdcd3 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -39,22 +39,6 @@
#define D_LOG(...) do { } while (0)
#endif
-#if defined(CONFIG_USER_ONLY)
-
-bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- CRISCPU *cpu = CRIS_CPU(cs);
-
- cs->exception_index = 0xaa;
- cpu->env.pregs[PR_EDA] = address;
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else /* !CONFIG_USER_ONLY */
-
-
static void cris_shift_ccs(CPUCRISState *env)
{
uint32_t ccs;
@@ -304,5 +288,3 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return ret;
}
-
-#endif /* !CONFIG_USER_ONLY */
diff --git a/target/cris/meson.build b/target/cris/meson.build
index 67c3793c85..c1e326d950 100644
--- a/target/cris/meson.build
+++ b/target/cris/meson.build
@@ -2,13 +2,16 @@ cris_ss = ss.source_set()
cris_ss.add(files(
'cpu.c',
'gdbstub.c',
- 'helper.c',
'op_helper.c',
'translate.c',
))
cris_softmmu_ss = ss.source_set()
-cris_softmmu_ss.add(files('mmu.c', 'machine.c'))
+cris_softmmu_ss.add(files(
+ 'helper.c',
+ 'machine.c',
+ 'mmu.c',
+))
target_arch += {'cris': cris_ss}
target_softmmu_arch += {'cris': cris_softmmu_ss}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (23 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 24/67] target/cris: Make cris_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
` (41 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Taylor Simpson, alex.bennee, laurent, imp
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hexagon linux-user.
Remove the code from cpu_loop that raises SIGSEGV.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hexagon/cpu_loop.c | 24 +-----------------------
target/hexagon/cpu.c | 23 -----------------------
2 files changed, 1 insertion(+), 46 deletions(-)
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index bee2a9e4ea..6b24cbaba9 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -28,8 +28,7 @@
void cpu_loop(CPUHexagonState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr, signum, sigcode;
- target_ulong sigaddr;
+ int trapnr;
target_ulong syscallnum;
target_ulong ret;
@@ -39,10 +38,6 @@ void cpu_loop(CPUHexagonState *env)
cpu_exec_end(cs);
process_queued_cpu_work(cs);
- signum = 0;
- sigcode = 0;
- sigaddr = 0;
-
switch (trapnr) {
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
@@ -65,12 +60,6 @@ void cpu_loop(CPUHexagonState *env)
env->gpr[0] = ret;
}
break;
- case HEX_EXCP_FETCH_NO_UPAGE:
- case HEX_EXCP_PRIV_NO_UREAD:
- case HEX_EXCP_PRIV_NO_UWRITE:
- signum = TARGET_SIGSEGV;
- sigcode = TARGET_SEGV_MAPERR;
- break;
case EXCP_ATOMIC:
cpu_exec_step_atomic(cs);
break;
@@ -79,17 +68,6 @@ void cpu_loop(CPUHexagonState *env)
trapnr);
exit(EXIT_FAILURE);
}
-
- if (signum) {
- target_siginfo_t info = {
- .si_signo = signum,
- .si_errno = 0,
- .si_code = sigcode,
- ._sifields._sigfault._addr = sigaddr
- };
- queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
- }
-
process_pending_signals(env);
}
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3338365c16..160a46a3d5 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -245,34 +245,11 @@ static void hexagon_cpu_init(Object *obj)
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
}
-static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
-#ifdef CONFIG_USER_ONLY
- switch (access_type) {
- case MMU_INST_FETCH:
- cs->exception_index = HEX_EXCP_FETCH_NO_UPAGE;
- break;
- case MMU_DATA_LOAD:
- cs->exception_index = HEX_EXCP_PRIV_NO_UREAD;
- break;
- case MMU_DATA_STORE:
- cs->exception_index = HEX_EXCP_PRIV_NO_UWRITE;
- break;
- }
- cpu_loop_exit_restore(cs, retaddr);
-#else
-#error System mode not implemented for Hexagon
-#endif
-}
-
#include "hw/core/tcg-cpu-ops.h"
static const struct TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
- .tlb_fill = hexagon_tlb_fill,
};
static void hexagon_cpu_class_init(ObjectClass *c, void *data)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (24 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 25/67] target/hexagon: Remove hexagon_cpu_tlb_fill Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
` (40 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
The fallback code in cpu_loop_exit_sigsegv is sufficient
for hppa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
This makes all of the code in mem_helper.c sysemu only,
so remove the ifdefs and move the file to hppa_softmmu_ss.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 2 +-
linux-user/hppa/cpu_loop.c | 16 ----------------
target/hppa/cpu.c | 2 +-
target/hppa/mem_helper.c | 15 ---------------
target/hppa/meson.build | 6 ++++--
5 files changed, 6 insertions(+), 35 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index d3cb7a279f..294fd7297f 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -323,10 +323,10 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
+#ifndef CONFIG_USER_ONLY
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-#ifndef CONFIG_USER_ONLY
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index 81607a9b27..e0a62deeb9 100644
--- a/linux-user/hppa/cpu_loop.c
+++ b/linux-user/hppa/cpu_loop.c
@@ -144,22 +144,6 @@ void cpu_loop(CPUHPPAState *env)
env->iaoq_f = env->gr[31];
env->iaoq_b = env->gr[31] + 4;
break;
- case EXCP_ITLB_MISS:
- case EXCP_DTLB_MISS:
- case EXCP_NA_ITLB_MISS:
- case EXCP_NA_DTLB_MISS:
- case EXCP_IMP:
- case EXCP_DMP:
- case EXCP_DMB:
- case EXCP_PAGE_REF:
- case EXCP_DMAR:
- case EXCP_DMPI:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_ACCERR;
- info._sifields._sigfault._addr = env->cr[CR_IOR];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_UNALIGN:
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 89cba9d7a2..23eb254228 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -145,9 +145,9 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
static const struct TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
- .tlb_fill = hppa_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = hppa_cpu_tlb_fill,
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.do_interrupt = hppa_cpu_do_interrupt,
.do_unaligned_access = hppa_cpu_do_unaligned_access,
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index afc5b56c3e..bf07445cd1 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -24,20 +24,6 @@
#include "hw/core/cpu.h"
#include "trace.h"
-#ifdef CONFIG_USER_ONLY
-bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- HPPACPU *cpu = HPPA_CPU(cs);
-
- /* ??? Test between data page fault and data memory protection trap,
- which would affect si_code. */
- cs->exception_index = EXCP_DMP;
- cpu->env.cr[CR_IOR] = address;
- cpu_loop_exit_restore(cs, retaddr);
-}
-#else
static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
{
int i;
@@ -392,4 +378,3 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr);
return ent ? ent->ar_type : -1;
}
-#endif /* CONFIG_USER_ONLY */
diff --git a/target/hppa/meson.build b/target/hppa/meson.build
index 8a7ff82efc..021e42a2d0 100644
--- a/target/hppa/meson.build
+++ b/target/hppa/meson.build
@@ -7,13 +7,15 @@ hppa_ss.add(files(
'gdbstub.c',
'helper.c',
'int_helper.c',
- 'mem_helper.c',
'op_helper.c',
'translate.c',
))
hppa_softmmu_ss = ss.source_set()
-hppa_softmmu_ss.add(files('machine.c'))
+hppa_softmmu_ss.add(files(
+ 'machine.c',
+ 'mem_helper.c',
+))
target_arch += {'hppa': hppa_ss}
target_softmmu_arch += {'hppa': hppa_softmmu_ss}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (25 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 26/67] target/hppa: Make hppa_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
` (39 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Record cr2, error_code, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
Use the maperr parameter to properly set PG_ERROR_P_MASK.
Reviewed by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/helper-tcg.h | 6 ++++++
target/i386/tcg/tcg-cpu.c | 3 ++-
target/i386/tcg/user/excp_helper.c | 23 +++++++++++++++++------
3 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
index 60ca09e95e..0a4401e917 100644
--- a/target/i386/tcg/helper-tcg.h
+++ b/target/i386/tcg/helper-tcg.h
@@ -43,9 +43,15 @@ bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
#endif
/* helper.c */
+#ifdef CONFIG_USER_ONLY
+void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#endif
void breakpoint_handler(CPUState *cs);
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 3ecfae34cb..6fdfdf9598 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -72,10 +72,11 @@ static const struct TCGCPUOps x86_tcg_ops = {
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.cpu_exec_enter = x86_cpu_exec_enter,
.cpu_exec_exit = x86_cpu_exec_exit,
- .tlb_fill = x86_cpu_tlb_fill,
#ifdef CONFIG_USER_ONLY
.fake_user_interrupt = x86_cpu_do_interrupt,
+ .record_sigsegv = x86_cpu_record_sigsegv,
#else
+ .tlb_fill = x86_cpu_tlb_fill,
.do_interrupt = x86_cpu_do_interrupt,
.cpu_exec_interrupt = x86_cpu_exec_interrupt,
.debug_excp_handler = breakpoint_handler,
diff --git a/target/i386/tcg/user/excp_helper.c b/target/i386/tcg/user/excp_helper.c
index a89b5228fd..cd507e2a1b 100644
--- a/target/i386/tcg/user/excp_helper.c
+++ b/target/i386/tcg/user/excp_helper.c
@@ -22,18 +22,29 @@
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
-bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
+ /*
+ * The error_code that hw reports as part of the exception frame
+ * is copied to linux sigcontext.err. The exception_index is
+ * copied to linux sigcontext.trapno. Short of inventing a new
+ * place to store the trapno, we cannot let our caller raise the
+ * signal and set exception_index to EXCP_INTERRUPT.
+ */
env->cr[2] = addr;
- env->error_code = (access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT;
- env->error_code |= PG_ERROR_U_MASK;
+ env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT)
+ | (maperr ? 0 : PG_ERROR_P_MASK)
+ | PG_ERROR_U_MASK;
cs->exception_index = EXCP0E_PAGE;
+
+ /* Disable do_interrupt_user. */
env->exception_is_int = 0;
env->exception_next_eip = -1;
- cpu_loop_exit_restore(cs, retaddr);
+
+ cpu_loop_exit_restore(cs, ra);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (26 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 27/67] target/i386: Implement x86_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
` (38 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for m68k linux-user.
Remove the code from cpu_loop that handled EXCP_ACCESS.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/m68k/cpu_loop.c | 10 ----------
target/m68k/cpu.c | 2 +-
target/m68k/helper.c | 6 +-----
3 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c
index ebf32be78f..790bd558c3 100644
--- a/linux-user/m68k/cpu_loop.c
+++ b/linux-user/m68k/cpu_loop.c
@@ -90,16 +90,6 @@ void cpu_loop(CPUM68KState *env)
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
- case EXCP_ACCESS:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->mmu.ar;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
case EXCP_DEBUG:
info.si_signo = TARGET_SIGTRAP;
info.si_errno = 0;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 66d22d1189..c7aeb7da9c 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -515,9 +515,9 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
static const struct TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
- .tlb_fill = m68k_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = m68k_cpu_tlb_fill,
.cpu_exec_interrupt = m68k_cpu_exec_interrupt,
.do_interrupt = m68k_cpu_do_interrupt,
.do_transaction_failed = m68k_cpu_transaction_failed,
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index 137a3e1a3d..5728e48585 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -978,16 +978,12 @@ void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
}
}
-#endif
-
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType qemu_access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
{
M68kCPU *cpu = M68K_CPU(cs);
CPUM68KState *env = &cpu->env;
-
-#ifndef CONFIG_USER_ONLY
hwaddr physical;
int prot;
int access_type;
@@ -1051,12 +1047,12 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
if (!(access_type & ACCESS_STORE)) {
env->mmu.ssw |= M68K_RW_040;
}
-#endif
cs->exception_index = EXCP_ACCESS;
env->mmu.ar = address;
cpu_loop_exit_restore(cs, retaddr);
}
+#endif /* !CONFIG_USER_ONLY */
uint32_t HELPER(bitrev)(uint32_t x)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (27 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 28/67] target/m68k: Make m68k_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
` (37 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
The fallback code in cpu_loop_exit_sigsegv is sufficient
for microblaze linux-user.
Remove the code from cpu_loop that handled the unnamed 0xaa exception.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 8 ++++----
linux-user/microblaze/cpu_loop.c | 10 ----------
target/microblaze/cpu.c | 2 +-
target/microblaze/helper.c | 13 +------------
4 files changed, 6 insertions(+), 27 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index b7a848bbae..e9cd0b88de 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -394,10 +394,6 @@ void mb_tcg_init(void);
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
-
typedef CPUMBState CPUArchState;
typedef MicroBlazeCPU ArchCPU;
@@ -415,6 +411,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
}
#if !defined(CONFIG_USER_ONLY)
+bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index 52222eb93f..a94467dd2d 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -37,16 +37,6 @@ void cpu_loop(CPUMBState *env)
process_queued_cpu_work(cs);
switch (trapnr) {
- case 0xaa:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = 0;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
case EXCP_INTERRUPT:
/* just indicate that signals should be handled asap */
break;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 15db277925..b9c888b87e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -365,9 +365,9 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
static const struct TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
- .tlb_fill = mb_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = mb_cpu_tlb_fill,
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
.do_interrupt = mb_cpu_do_interrupt,
.do_transaction_failed = mb_cpu_transaction_failed,
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index dd2aecd1d5..a607fe68e5 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -24,18 +24,7 @@
#include "qemu/host-utils.h"
#include "exec/log.h"
-#if defined(CONFIG_USER_ONLY)
-
-bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- cs->exception_index = 0xaa;
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else /* !CONFIG_USER_ONLY */
-
+#ifndef CONFIG_USER_ONLY
static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
MMUAccessType access_type)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (28 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 29/67] target/microblaze: Make mb_cpu_tlb_fill " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:40 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
` (36 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for mips linux-user.
This means we can remove tcg/user/tlb_helper.c entirely.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/tcg-internal.h | 7 ++--
linux-user/mips/cpu_loop.c | 11 ------
target/mips/cpu.c | 2 +-
target/mips/tcg/user/tlb_helper.c | 59 -------------------------------
target/mips/tcg/meson.build | 3 --
target/mips/tcg/user/meson.build | 3 --
6 files changed, 5 insertions(+), 80 deletions(-)
delete mode 100644 target/mips/tcg/user/tlb_helper.c
delete mode 100644 target/mips/tcg/user/meson.build
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index bad3deb611..466768aec4 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -18,9 +18,6 @@
void mips_tcg_init(void);
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr) QEMU_NORETURN;
@@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr);
void cpu_mips_tlb_flush(CPUMIPSState *env);
+bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
#endif /* !CONFIG_USER_ONLY */
#endif
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index cb03fb066b..b735c99a24 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -158,17 +158,6 @@ done_syscall:
}
env->active_tc.gpr[2] = ret;
break;
- case EXCP_TLBL:
- case EXCP_TLBS:
- case EXCP_AdEL:
- case EXCP_AdES:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->CP0_BadVAddr;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_CpU:
case EXCP_RI:
info.si_signo = TARGET_SIGILL;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 00e0c55d0e..4aae23934b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
static const struct TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
- .tlb_fill = mips_cpu_tlb_fill,
#if !defined(CONFIG_USER_ONLY)
+ .tlb_fill = mips_cpu_tlb_fill,
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
.do_interrupt = mips_cpu_do_interrupt,
.do_transaction_failed = mips_cpu_do_transaction_failed,
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c
deleted file mode 100644
index 210c6d529e..0000000000
--- a/target/mips/tcg/user/tlb_helper.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * MIPS TLB (Translation lookaside buffer) helpers.
- *
- * Copyright (c) 2004-2005 Jocelyn Mayer
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2.1 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-#include "qemu/osdep.h"
-
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "internal.h"
-
-static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
- MMUAccessType access_type)
-{
- CPUState *cs = env_cpu(env);
-
- env->error_code = 0;
- if (access_type == MMU_INST_FETCH) {
- env->error_code |= EXCP_INST_NOTAVAIL;
- }
-
- /* Reference to kernel address from user mode or supervisor mode */
- /* Reference to supervisor address from user mode */
- if (access_type == MMU_DATA_STORE) {
- cs->exception_index = EXCP_AdES;
- } else {
- cs->exception_index = EXCP_AdEL;
- }
-
- /* Raise exception */
- if (!(env->hflags & MIPS_HFLAG_DM)) {
- env->CP0_BadVAddr = address;
- }
-}
-
-bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- MIPSCPU *cpu = MIPS_CPU(cs);
- CPUMIPSState *env = &cpu->env;
-
- /* data access */
- raise_mmu_exception(env, address, access_type);
- do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
-}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 8f6f7508b6..98003779ae 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'mxu_translate.c',
))
-if have_user
- subdir('user')
-endif
if have_system
subdir('sysemu')
endif
diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build
deleted file mode 100644
index 79badcd321..0000000000
--- a/target/mips/tcg/user/meson.build
+++ /dev/null
@@ -1,3 +0,0 @@
-mips_user_ss.add(files(
- 'tlb_helper.c',
-))
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill sysemu only
2021-10-15 4:10 ` [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
@ 2021-10-15 18:40 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:40 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 7097 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for mips linux-user.
>
> This means we can remove tcg/user/tlb_helper.c entirely.
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/tcg/tcg-internal.h | 7 ++--
> linux-user/mips/cpu_loop.c | 11 ------
> target/mips/cpu.c | 2 +-
> target/mips/tcg/user/tlb_helper.c | 59 -------------------------------
> target/mips/tcg/meson.build | 3 --
> target/mips/tcg/user/meson.build | 3 --
> 6 files changed, 5 insertions(+), 80 deletions(-)
> delete mode 100644 target/mips/tcg/user/tlb_helper.c
> delete mode 100644 target/mips/tcg/user/meson.build
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
We do have mips support in bsd-user fork, but it's unclear how long we'll
continue
that support, though. This seems like it won't present a big problem for us
should
we continue that support, though (at least for FreeBSD). The usual
$(OTHER)BSD
caveats apply.
Warner
> diff --git a/target/mips/tcg/tcg-internal.h
> b/target/mips/tcg/tcg-internal.h
> index bad3deb611..466768aec4 100644
> --- a/target/mips/tcg/tcg-internal.h
> +++ b/target/mips/tcg/tcg-internal.h
> @@ -18,9 +18,6 @@
> void mips_tcg_init(void);
>
> void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock
> *tb);
> -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr);
> void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> uintptr_t retaddr) QEMU_NORETURN;
> @@ -60,6 +57,10 @@ void mips_cpu_do_transaction_failed(CPUState *cs,
> hwaddr physaddr,
> MemTxResult response, uintptr_t
> retaddr);
> void cpu_mips_tlb_flush(CPUMIPSState *env);
>
> +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr);
> +
> #endif /* !CONFIG_USER_ONLY */
>
> #endif
> diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
> index cb03fb066b..b735c99a24 100644
> --- a/linux-user/mips/cpu_loop.c
> +++ b/linux-user/mips/cpu_loop.c
> @@ -158,17 +158,6 @@ done_syscall:
> }
> env->active_tc.gpr[2] = ret;
> break;
> - case EXCP_TLBL:
> - case EXCP_TLBS:
> - case EXCP_AdEL:
> - case EXCP_AdES:
> - info.si_signo = TARGET_SIGSEGV;
> - info.si_errno = 0;
> - /* XXX: check env->error_code */
> - info.si_code = TARGET_SEGV_MAPERR;
> - info._sifields._sigfault._addr = env->CP0_BadVAddr;
> - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> - break;
> case EXCP_CpU:
> case EXCP_RI:
> info.si_signo = TARGET_SIGILL;
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 00e0c55d0e..4aae23934b 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -539,9 +539,9 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
> static const struct TCGCPUOps mips_tcg_ops = {
> .initialize = mips_tcg_init,
> .synchronize_from_tb = mips_cpu_synchronize_from_tb,
> - .tlb_fill = mips_cpu_tlb_fill,
>
> #if !defined(CONFIG_USER_ONLY)
> + .tlb_fill = mips_cpu_tlb_fill,
> .cpu_exec_interrupt = mips_cpu_exec_interrupt,
> .do_interrupt = mips_cpu_do_interrupt,
> .do_transaction_failed = mips_cpu_do_transaction_failed,
> diff --git a/target/mips/tcg/user/tlb_helper.c
> b/target/mips/tcg/user/tlb_helper.c
> deleted file mode 100644
> index 210c6d529e..0000000000
> --- a/target/mips/tcg/user/tlb_helper.c
> +++ /dev/null
> @@ -1,59 +0,0 @@
> -/*
> - * MIPS TLB (Translation lookaside buffer) helpers.
> - *
> - * Copyright (c) 2004-2005 Jocelyn Mayer
> - *
> - * This library is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU Lesser General Public
> - * License as published by the Free Software Foundation; either
> - * version 2.1 of the License, or (at your option) any later version.
> - *
> - * This library is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> - * Lesser General Public License for more details.
> - *
> - * You should have received a copy of the GNU Lesser General Public
> - * License along with this library; if not, see <
> http://www.gnu.org/licenses/>.
> - */
> -#include "qemu/osdep.h"
> -
> -#include "cpu.h"
> -#include "exec/exec-all.h"
> -#include "internal.h"
> -
> -static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> - MMUAccessType access_type)
> -{
> - CPUState *cs = env_cpu(env);
> -
> - env->error_code = 0;
> - if (access_type == MMU_INST_FETCH) {
> - env->error_code |= EXCP_INST_NOTAVAIL;
> - }
> -
> - /* Reference to kernel address from user mode or supervisor mode */
> - /* Reference to supervisor address from user mode */
> - if (access_type == MMU_DATA_STORE) {
> - cs->exception_index = EXCP_AdES;
> - } else {
> - cs->exception_index = EXCP_AdEL;
> - }
> -
> - /* Raise exception */
> - if (!(env->hflags & MIPS_HFLAG_DM)) {
> - env->CP0_BadVAddr = address;
> - }
> -}
> -
> -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr)
> -{
> - MIPSCPU *cpu = MIPS_CPU(cs);
> - CPUMIPSState *env = &cpu->env;
> -
> - /* data access */
> - raise_mmu_exception(env, address, access_type);
> - do_raise_exception_err(env, cs->exception_index, env->error_code,
> retaddr);
> -}
> diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
> index 8f6f7508b6..98003779ae 100644
> --- a/target/mips/tcg/meson.build
> +++ b/target/mips/tcg/meson.build
> @@ -28,9 +28,6 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
> 'mxu_translate.c',
> ))
>
> -if have_user
> - subdir('user')
> -endif
> if have_system
> subdir('sysemu')
> endif
> diff --git a/target/mips/tcg/user/meson.build
> b/target/mips/tcg/user/meson.build
> deleted file mode 100644
> index 79badcd321..0000000000
> --- a/target/mips/tcg/user/meson.build
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -mips_user_ss.add(files(
> - 'tlb_helper.c',
> -))
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 8756 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (29 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 30/67] target/mips: Make mips_cpu_tlb_fill " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Richard Henderson
` (35 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Because the linux-user kuser page handling is currently implemented
by detecting magic addresses in the unnamed 0xaa trap, we cannot
simply remove nios2_cpu_tlb_fill and rely on the fallback code.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 6 ++++++
target/nios2/cpu.c | 6 ++++--
target/nios2/helper.c | 7 ++++---
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index a80587338a..1a69ed7a49 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -218,9 +218,15 @@ static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
MMU_SUPERVISOR_IDX;
}
+#ifdef CONFIG_USER_ONLY
+void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+#endif
static inline int cpu_interrupts_enabled(CPUNios2State *env)
{
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 947bb09bc1..421cad114a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -220,9 +220,11 @@ static const struct SysemuCPUOps nios2_sysemu_ops = {
static const struct TCGCPUOps nios2_tcg_ops = {
.initialize = nios2_tcg_init,
- .tlb_fill = nios2_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = nios2_cpu_record_sigsegv,
+#else
+ .tlb_fill = nios2_cpu_tlb_fill,
.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
.do_interrupt = nios2_cpu_do_interrupt,
.do_unaligned_access = nios2_cpu_do_unaligned_access,
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 53be8398e9..e5c98650e1 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -38,10 +38,11 @@ void nios2_cpu_do_interrupt(CPUState *cs)
env->regs[R_EA] = env->regs[R_PC] + 4;
}
-bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
+ /* FIXME: Disentangle kuser page from linux-user sigsegv handling. */
cs->exception_index = 0xaa;
cpu_loop_exit_restore(cs, retaddr);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (30 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 31/67] target/nios2: Implement nios2_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
` (34 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Stafford Horne, alex.bennee, laurent, imp
The kernel vectors both of these through unhandled_exception, which
results in force_sig(SIGSEGV). This isn't very useful for userland
when enabling overflow traps or fpu traps, but c'est la vie.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/openrisc/cpu_loop.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c
index f6360db47c..de5417a262 100644
--- a/linux-user/openrisc/cpu_loop.c
+++ b/linux-user/openrisc/cpu_loop.c
@@ -56,13 +56,17 @@ void cpu_loop(CPUOpenRISCState *env)
break;
case EXCP_DPF:
case EXCP_IPF:
- case EXCP_RANGE:
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
info.si_code = TARGET_SEGV_MAPERR;
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_RANGE:
+ case EXCP_FPE:
+ /* ??? The kernel vectors both of these to unhandled_exception. */
+ force_sig(TARGET_SIGSEGV);
+ break;
case EXCP_ALIGN:
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
@@ -77,13 +81,6 @@ void cpu_loop(CPUOpenRISCState *env)
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
- case EXCP_FPE:
- info.si_signo = TARGET_SIGFPE;
- info.si_errno = 0;
- info.si_code = 0;
- info._sifields._sigfault._addr = env->pc;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_INTERRUPT:
/* We processed the pending cpu work above. */
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (31 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 32/67] linux-user/openrisc: Adjust signal for EXCP_RANGE, EXCP_FPE Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
` (33 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient for
openrisc linux-user.
This makes all of the code in mmu.c sysemu only, so remove
the ifdefs and move the file to openrisc_softmmu_ss.
Remove the code from cpu_loop that handled EXCP_DPF.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/cpu.h | 7 ++++---
linux-user/openrisc/cpu_loop.c | 8 --------
target/openrisc/cpu.c | 2 +-
target/openrisc/mmu.c | 9 ---------
target/openrisc/meson.build | 2 +-
5 files changed, 6 insertions(+), 22 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 187a4a114e..ee069b080c 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -317,14 +317,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
-bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#define cpu_list cpu_openrisc_list
#ifndef CONFIG_USER_ONLY
+bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
extern const VMStateDescription vmstate_openrisc_cpu;
void openrisc_cpu_do_interrupt(CPUState *cpu);
diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c
index de5417a262..fb37fb7651 100644
--- a/linux-user/openrisc/cpu_loop.c
+++ b/linux-user/openrisc/cpu_loop.c
@@ -54,14 +54,6 @@ void cpu_loop(CPUOpenRISCState *env)
cpu_set_gpr(env, 11, ret);
}
break;
- case EXCP_DPF:
- case EXCP_IPF:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->pc;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_RANGE:
case EXCP_FPE:
/* ??? The kernel vectors both of these to unhandled_exception. */
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 27cb04152f..dfbafc5236 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -186,9 +186,9 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
- .tlb_fill = openrisc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = openrisc_cpu_tlb_fill,
.cpu_exec_interrupt = openrisc_cpu_exec_interrupt,
.do_interrupt = openrisc_cpu_do_interrupt,
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 94df8c7bef..e561ef245b 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -23,11 +23,8 @@
#include "exec/exec-all.h"
#include "exec/gdbstub.h"
#include "qemu/host-utils.h"
-#ifndef CONFIG_USER_ONLY
#include "hw/loader.h"
-#endif
-#ifndef CONFIG_USER_ONLY
static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
target_ulong address)
{
@@ -94,7 +91,6 @@ static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
}
}
-#endif
static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
int exception)
@@ -112,8 +108,6 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int excp = EXCP_DPF;
-
-#ifndef CONFIG_USER_ONLY
int prot;
hwaddr phys_addr;
@@ -138,13 +132,11 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
if (probe) {
return false;
}
-#endif
raise_mmu_exception(cpu, addr, excp);
cpu_loop_exit_restore(cs, retaddr);
}
-#ifndef CONFIG_USER_ONLY
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
@@ -177,4 +169,3 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return phys_addr;
}
}
-#endif
diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build
index e445dec4a0..84322086ec 100644
--- a/target/openrisc/meson.build
+++ b/target/openrisc/meson.build
@@ -10,7 +10,6 @@ openrisc_ss.add(files(
'fpu_helper.c',
'gdbstub.c',
'interrupt_helper.c',
- 'mmu.c',
'sys_helper.c',
'translate.c',
))
@@ -19,6 +18,7 @@ openrisc_softmmu_ss = ss.source_set()
openrisc_softmmu_ss.add(files(
'interrupt.c',
'machine.c',
+ 'mmu.c',
))
target_arch += {'openrisc': openrisc_ss}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (32 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 33/67] target/openrisc: Make openrisc_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:45 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
` (32 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Record DAR, DSISR, and exception_index. That last means
that we must exit to cpu_loop ourselves, instead of letting
exception_index being overwritten.
This is exactly what the user-mode ppc_cpu_tlb_fill does,
so simply rename it as ppc_cpu_record_sigsegv.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 3 ---
target/ppc/internal.h | 9 +++++++++
target/ppc/cpu_init.c | 6 ++++--
target/ppc/user_only_helper.c | 15 +++++++++++----
4 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index baa4e7c34d..2242d57718 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu;
/*****************************************************************************/
void ppc_translate_init(void);
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 55284369f5..339974b7d8 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)
#define PTE_PTEM_MASK 0x7FFFFFBF
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
+#ifdef CONFIG_USER_ONLY
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t ra);
+#else
+bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+#endif
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 6aad01d1d3..ec8da08f0b 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
- .tlb_fill = ppc_cpu_tlb_fill,
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = ppc_cpu_record_sigsegv,
+#else
+ .tlb_fill = ppc_cpu_tlb_fill,
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c
index aa3f867596..7ff76f7a06 100644
--- a/target/ppc/user_only_helper.c
+++ b/target/ppc/user_only_helper.c
@@ -21,16 +21,23 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
+#include "internal.h"
-
-bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
int exception, error_code;
+ /*
+ * Both DSISR and the "trap number" (exception vector offset,
+ * looked up from exception_index) are present in the linux-user
+ * signal frame.
+ * FIXME: we don't actually populate the trap number properly.
+ * It would be easiest to fill in an env->trap value now.
+ */
if (access_type == MMU_INST_FETCH) {
exception = POWERPC_EXCP_ISI;
error_code = 0x40000000;
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv
2021-10-15 4:10 ` [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 18:45 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:45 UTC (permalink / raw)
To: Richard Henderson
Cc: Philippe Mathieu-Daudé, Alex Bennée, QEMU Developers,
Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 4505 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Record DAR, DSISR, and exception_index. That last means
> that we must exit to cpu_loop ourselves, instead of letting
> exception_index being overwritten.
>
> This is exactly what the user-mode ppc_cpu_tlb_fill does,
> so simply rename it as ppc_cpu_record_sigsegv.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/ppc/cpu.h | 3 ---
> target/ppc/internal.h | 9 +++++++++
> target/ppc/cpu_init.c | 6 ++++--
> target/ppc/user_only_helper.c | 15 +++++++++++----
> 4 files changed, 24 insertions(+), 9 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index baa4e7c34d..2242d57718 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1279,9 +1279,6 @@ extern const VMStateDescription vmstate_ppc_cpu;
>
>
> /*****************************************************************************/
> void ppc_translate_init(void);
> -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr);
>
> #if !defined(CONFIG_USER_ONLY)
> void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 55284369f5..339974b7d8 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -283,5 +283,14 @@ static inline void pte_invalidate(target_ulong *pte0)
> #define PTE_PTEM_MASK 0x7FFFFFBF
> #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
>
> +#ifdef CONFIG_USER_ONLY
> +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
> + MMUAccessType access_type,
> + bool maperr, uintptr_t ra);
> +#else
> +bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr);
> +#endif
>
> #endif /* PPC_INTERNAL_H */
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 6aad01d1d3..ec8da08f0b 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -9014,9 +9014,11 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
>
> static const struct TCGCPUOps ppc_tcg_ops = {
> .initialize = ppc_translate_init,
> - .tlb_fill = ppc_cpu_tlb_fill,
>
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + .record_sigsegv = ppc_cpu_record_sigsegv,
> +#else
> + .tlb_fill = ppc_cpu_tlb_fill,
> .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
> .do_interrupt = ppc_cpu_do_interrupt,
> .cpu_exec_enter = ppc_cpu_exec_enter,
> diff --git a/target/ppc/user_only_helper.c b/target/ppc/user_only_helper.c
> index aa3f867596..7ff76f7a06 100644
> --- a/target/ppc/user_only_helper.c
> +++ b/target/ppc/user_only_helper.c
> @@ -21,16 +21,23 @@
> #include "qemu/osdep.h"
> #include "cpu.h"
> #include "exec/exec-all.h"
> +#include "internal.h"
>
> -
> -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> - MMUAccessType access_type, int mmu_idx,
> - bool probe, uintptr_t retaddr)
> +void ppc_cpu_record_sigsegv(CPUState *cs, vaddr address,
> + MMUAccessType access_type,
> + bool maperr, uintptr_t retaddr)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = &cpu->env;
> int exception, error_code;
>
> + /*
> + * Both DSISR and the "trap number" (exception vector offset,
> + * looked up from exception_index) are present in the linux-user
> + * signal frame.
> + * FIXME: we don't actually populate the trap number properly.
> + * It would be easiest to fill in an env->trap value now.
> + */
>
I think the same concerns apply to bsd-user, though
the details differ since trap frames only fill in information
relevant to the specific trap type. This may require some
refinement in the future when it's time to upstream bsd-user
ppc support. I'll revisit this, though, when that time comes.
Warner
> if (access_type == MMU_INST_FETCH) {
> exception = POWERPC_EXCP_ISI;
> error_code = 0x40000000;
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 5875 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (33 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 34/67] target/ppc: Implement ppc_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:45 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
` (31 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for riscv linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/riscv/cpu_loop.c | 7 -------
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 21 +--------------------
3 files changed, 2 insertions(+), 28 deletions(-)
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 9859a366e4..aef019b1c8 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env)
sigcode = TARGET_TRAP_BRKPT;
sigaddr = env->pc;
break;
- case RISCV_EXCP_INST_PAGE_FAULT:
- case RISCV_EXCP_LOAD_PAGE_FAULT:
- case RISCV_EXCP_STORE_PAGE_FAULT:
- signum = TARGET_SIGSEGV;
- sigcode = TARGET_SEGV_MAPERR;
- sigaddr = env->badaddr;
- break;
case RISCV_EXCP_SEMIHOST:
env->gpr[xA0] = do_common_semihosting(cs);
env->pc += 4;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..2ab89a3f70 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
static const struct TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .tlb_fill = riscv_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = riscv_cpu_tlb_fill,
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c..b520d6fc78 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
riscv_cpu_two_stage_lookup(mmu_idx);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
-#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
-#ifndef CONFIG_USER_ONLY
vaddr im_address;
hwaddr pa = 0;
int prot, prot2, prot_pmp;
@@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
return true;
-
-#else
- switch (access_type) {
- case MMU_INST_FETCH:
- cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
- break;
- case MMU_DATA_LOAD:
- cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
- break;
- case MMU_DATA_STORE:
- cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
- break;
- default:
- g_assert_not_reached();
- }
- env->badaddr = address;
- cpu_loop_exit_restore(cs, retaddr);
-#endif
}
+#endif /* !CONFIG_USER_ONLY */
/*
* Handle Traps
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only
2021-10-15 4:10 ` [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 18:45 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:45 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, Philippe Mathieu-Daudé, Alex Bennée,
QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 3718 bytes --]
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> The fallback code in cpu_loop_exit_sigsegv is sufficient
> for riscv linux-user.
>
> Remove the code from cpu_loop that raised SIGSEGV.
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/riscv/cpu_loop.c | 7 -------
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 21 +--------------------
> 3 files changed, 2 insertions(+), 28 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 9859a366e4..aef019b1c8 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -87,13 +87,6 @@ void cpu_loop(CPURISCVState *env)
> sigcode = TARGET_TRAP_BRKPT;
> sigaddr = env->pc;
> break;
> - case RISCV_EXCP_INST_PAGE_FAULT:
> - case RISCV_EXCP_LOAD_PAGE_FAULT:
> - case RISCV_EXCP_STORE_PAGE_FAULT:
> - signum = TARGET_SIGSEGV;
> - sigcode = TARGET_SEGV_MAPERR;
> - sigaddr = env->badaddr;
> - break;
> case RISCV_EXCP_SEMIHOST:
> env->gpr[xA0] = do_common_semihosting(cs);
> env->pc += 4;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1d69d1887e..2ab89a3f70 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -653,9 +653,9 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
> static const struct TCGCPUOps riscv_tcg_ops = {
> .initialize = riscv_translate_init,
> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> - .tlb_fill = riscv_cpu_tlb_fill,
>
> #ifndef CONFIG_USER_ONLY
> + .tlb_fill = riscv_cpu_tlb_fill,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .do_interrupt = riscv_cpu_do_interrupt,
> .do_transaction_failed = riscv_cpu_do_transaction_failed,
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d41d5cd27c..b520d6fc78 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -748,7 +748,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
> addr,
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(env, cs->exception_index, retaddr);
> }
> -#endif /* !CONFIG_USER_ONLY */
>
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> @@ -756,7 +755,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -#ifndef CONFIG_USER_ONLY
> vaddr im_address;
> hwaddr pa = 0;
> int prot, prot2, prot_pmp;
> @@ -888,25 +886,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,
> int size,
> }
>
> return true;
> -
> -#else
> - switch (access_type) {
> - case MMU_INST_FETCH:
> - cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
> - break;
> - case MMU_DATA_LOAD:
> - cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
> - break;
> - case MMU_DATA_STORE:
> - cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - env->badaddr = address;
> - cpu_loop_exit_restore(cs, retaddr);
> -#endif
> }
> +#endif /* !CONFIG_USER_ONLY */
>
> /*
> * Handle Traps
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 4877 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (34 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 35/67] target/riscv: Make riscv_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
` (30 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Not sure why the user-only code wasn't rewritten to use
probe_access_flags at the same time that the sysemu code
was converted. For the purpose of user-only, this is an
exact replacement.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/mem_helper.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 17e3f83641..362a30d99e 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -141,20 +141,12 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx,
bool nonfault, void **phost, uintptr_t ra)
{
+#if defined(CONFIG_USER_ONLY)
+ return probe_access_flags(env, addr, access_type, mmu_idx,
+ nonfault, phost, ra);
+#else
int flags;
-#if defined(CONFIG_USER_ONLY)
- flags = page_get_flags(addr);
- if (!(flags & (access_type == MMU_DATA_LOAD ? PAGE_READ : PAGE_WRITE_ORG))) {
- env->__excp_addr = addr;
- flags = (flags & PAGE_VALID) ? PGM_PROTECTION : PGM_ADDRESSING;
- if (nonfault) {
- return flags;
- }
- tcg_s390_program_interrupt(env, flags, ra);
- }
- *phost = g2h(env_cpu(env), addr);
-#else
/*
* For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
* to detect if there was an exception during tlb_fill().
@@ -173,8 +165,8 @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
(access_type == MMU_DATA_STORE
? BP_MEM_WRITE : BP_MEM_READ), ra);
}
-#endif
return 0;
+#endif
}
static int access_prepare_nf(S390Access *access, CPUS390XState *env,
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (35 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 36/67] target/s390x: Use probe_access_flags in s390_probe_access Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
` (29 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
Move the masking of the address from cpu_loop into
s390_cpu_record_sigsegv -- this is governed by hw, not linux.
This does mean we have to raise our own exception, rather
than return to the fallback.
Use maperr to choose between PGM_PROTECTION and PGM_ADDRESSING.
Use the appropriate si_code for each in cpu_loop.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/s390x-internal.h | 13 ++++++++++---
linux-user/s390x/cpu_loop.c | 13 ++++++-------
target/s390x/cpu.c | 6 ++++--
target/s390x/tcg/excp_helper.c | 18 +++++++++++-------
4 files changed, 31 insertions(+), 19 deletions(-)
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 27d4a03ca1..163aa4f94a 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -270,13 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
void s390x_cpu_debug_excp_handler(CPUState *cs);
void s390_cpu_do_interrupt(CPUState *cpu);
bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
-bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr) QEMU_NORETURN;
+#ifdef CONFIG_USER_ONLY
+void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr);
+#else
+bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+#endif
+
/* fpu_helper.c */
uint32_t set_cc_nz_f32(float32 v);
diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c
index 69b69981f6..d089c8417e 100644
--- a/linux-user/s390x/cpu_loop.c
+++ b/linux-user/s390x/cpu_loop.c
@@ -24,8 +24,6 @@
#include "cpu_loop-common.h"
#include "signal-common.h"
-/* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */
-#define S390X_FAIL_ADDR_MASK -4096LL
static int get_pgm_data_si_code(int dxc_code)
{
@@ -111,12 +109,13 @@ void cpu_loop(CPUS390XState *env)
n = TARGET_ILL_ILLOPC;
goto do_signal_pc;
case PGM_PROTECTION:
+ force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_ACCERR,
+ env->__excp_addr);
+ break;
case PGM_ADDRESSING:
- sig = TARGET_SIGSEGV;
- /* XXX: check env->error_code */
- n = TARGET_SEGV_MAPERR;
- addr = env->__excp_addr & S390X_FAIL_ADDR_MASK;
- goto do_signal;
+ force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR,
+ env->__excp_addr);
+ break;
case PGM_EXECUTE:
case PGM_SPECIFICATION:
case PGM_SPECIAL_OP:
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7b7b05f1d3..593dda75c4 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -266,9 +266,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
static const struct TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
- .tlb_fill = s390_cpu_tlb_fill,
-#if !defined(CONFIG_USER_ONLY)
+#ifdef CONFIG_USER_ONLY
+ .record_sigsegv = s390_cpu_record_sigsegv,
+#else
+ .tlb_fill = s390_cpu_tlb_fill,
.cpu_exec_interrupt = s390_cpu_exec_interrupt,
.do_interrupt = s390_cpu_do_interrupt,
.debug_excp_handler = s390x_cpu_debug_excp_handler,
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index 3d6662a53c..b923d080fc 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -89,16 +89,20 @@ void s390_cpu_do_interrupt(CPUState *cs)
cs->exception_index = -1;
}
-bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
+void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
+ MMUAccessType access_type,
+ bool maperr, uintptr_t retaddr)
{
S390CPU *cpu = S390_CPU(cs);
- trigger_pgm_exception(&cpu->env, PGM_ADDRESSING);
- /* On real machines this value is dropped into LowMem. Since this
- is userland, simply put this someplace that cpu_loop can find it. */
- cpu->env.__excp_addr = address;
+ trigger_pgm_exception(&cpu->env, maperr ? PGM_ADDRESSING : PGM_PROTECTION);
+ /*
+ * On real machines this value is dropped into LowMem. Since this
+ * is userland, simply put this someplace that cpu_loop can find it.
+ * S390 only gives the page of the fault, not the exact address.
+ * C.f. the construction of TEC in mmu_translate().
+ */
+ cpu->env.__excp_addr = address & TARGET_PAGE_MASK;
cpu_loop_exit_restore(cs, retaddr);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (36 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 37/67] target/s390x: Implement s390_cpu_record_sigsegv Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
` (28 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sh4 linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/cpu.h | 6 +++---
linux-user/sh4/cpu_loop.c | 8 --------
target/sh4/cpu.c | 2 +-
target/sh4/helper.c | 9 +--------
4 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dc81406646..4cfb109f56 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -213,12 +213,12 @@ void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
uintptr_t retaddr) QEMU_NORETURN;
void sh4_translate_init(void);
+void sh4_cpu_list(void);
+
+#if !defined(CONFIG_USER_ONLY)
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-
-void sh4_cpu_list(void);
-#if !defined(CONFIG_USER_ONLY)
void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
index 65b8972e3c..ac9b01840c 100644
--- a/linux-user/sh4/cpu_loop.c
+++ b/linux-user/sh4/cpu_loop.c
@@ -65,14 +65,6 @@ void cpu_loop(CPUSH4State *env)
info.si_code = TARGET_TRAP_BRKPT;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
- case 0xa0:
- case 0xc0:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->tea;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_ATOMIC:
cpu_exec_step_atomic(cs);
arch_interrupt = false;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 2047742d03..06b2691dc4 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -236,9 +236,9 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
static const struct TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
- .tlb_fill = superh_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = superh_cpu_tlb_fill,
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
.do_interrupt = superh_cpu_do_interrupt,
.do_unaligned_access = superh_cpu_do_unaligned_access,
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 53cb9c3b63..6a620e36fc 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -796,8 +796,6 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
-#endif /* !CONFIG_USER_ONLY */
-
bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -806,11 +804,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPUSH4State *env = &cpu->env;
int ret;
-#ifdef CONFIG_USER_ONLY
- ret = (access_type == MMU_DATA_STORE ? MMU_DTLB_VIOLATION_WRITE :
- access_type == MMU_INST_FETCH ? MMU_ITLB_VIOLATION :
- MMU_DTLB_VIOLATION_READ);
-#else
target_ulong physical;
int prot;
@@ -829,7 +822,6 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
env->pteh = (env->pteh & PTEH_ASID_MASK) | (address & PTEH_VPN_MASK);
}
-#endif
env->tea = address;
switch (ret) {
@@ -868,3 +860,4 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
cpu_loop_exit_restore(cs, retaddr);
}
+#endif /* !CONFIG_USER_ONLY */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (37 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 38/67] target/sh4: Make sh4_cpu_tlb_fill sysemu only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
` (27 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel
Cc: Mark Cave-Ayland, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for sparc linux-user.
This makes all of the code in mmu_helper.c sysemu only, so remove
the ifdefs and move the file to sparc_softmmu_ss. Remove the code
from cpu_loop that handled TT_DFAULT and TT_TFAULT.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sparc/cpu_loop.c | 25 -------------------------
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 25 -------------------------
target/sparc/meson.build | 2 +-
4 files changed, 2 insertions(+), 52 deletions(-)
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index ad29b4eb6a..0ba65e431c 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -219,17 +219,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_WIN_UNF: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = env->mmuregs[4];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#else
case TT_SPILL: /* window overflow */
save_window(env);
@@ -237,20 +226,6 @@ void cpu_loop (CPUSPARCState *env)
case TT_FILL: /* window underflow */
restore_window(env);
break;
- case TT_TFAULT:
- case TT_DFAULT:
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
- if (trapnr == TT_DFAULT)
- info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
- else
- info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- }
- break;
#ifndef TARGET_ABI32
case 0x16e:
flush_windows(env);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 21dd27796d..55268ed2a1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -865,9 +865,9 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const struct TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
- .tlb_fill = sparc_cpu_tlb_fill,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = sparc_cpu_tlb_fill,
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index a44473a1c7..2ad47391d0 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -25,30 +25,6 @@
/* Sparc MMU emulation */
-#if defined(CONFIG_USER_ONLY)
-
-bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
- if (access_type == MMU_INST_FETCH) {
- cs->exception_index = TT_TFAULT;
- } else {
- cs->exception_index = TT_DFAULT;
-#ifdef TARGET_SPARC64
- env->dmmu.mmuregs[4] = address;
-#else
- env->mmuregs[4] = address;
-#endif
- }
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else
-
#ifndef TARGET_SPARC64
/*
* Sparc V8 Reference MMU (SRMMU)
@@ -926,4 +902,3 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
-#endif
diff --git a/target/sparc/meson.build b/target/sparc/meson.build
index a3638b9503..a801802ee2 100644
--- a/target/sparc/meson.build
+++ b/target/sparc/meson.build
@@ -6,7 +6,6 @@ sparc_ss.add(files(
'gdbstub.c',
'helper.c',
'ldst_helper.c',
- 'mmu_helper.c',
'translate.c',
'win_helper.c',
))
@@ -16,6 +15,7 @@ sparc_ss.add(when: 'TARGET_SPARC64', if_true: files('int64_helper.c', 'vis_helpe
sparc_softmmu_ss = ss.source_set()
sparc_softmmu_ss.add(files(
'machine.c',
+ 'mmu_helper.c',
'monitor.c',
))
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill sysemu only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (38 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 39/67] target/sparc: Make sparc_cpu_tlb_fill " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
` (26 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel
Cc: Max Filippov, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
The fallback code in cpu_loop_exit_sigsegv is sufficient
for xtensa linux-user.
Remove the code from cpu_loop that raised SIGSEGV.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/cpu.h | 2 +-
linux-user/xtensa/cpu_loop.c | 9 ---------
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 22 +---------------------
4 files changed, 3 insertions(+), 32 deletions(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index f9a510ca46..02143f2f77 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -563,10 +563,10 @@ struct XtensaCPU {
};
+#ifndef CONFIG_USER_ONLY
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_interrupt(CPUState *cpu);
bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c
index 622afbcd34..a83490ab35 100644
--- a/linux-user/xtensa/cpu_loop.c
+++ b/linux-user/xtensa/cpu_loop.c
@@ -226,15 +226,6 @@ void cpu_loop(CPUXtensaState *env)
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
- case LOAD_PROHIBITED_CAUSE:
- case STORE_PROHIBITED_CAUSE:
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- info.si_code = TARGET_SEGV_ACCERR;
- info._sifields._sigfault._addr = env->sregs[EXCVADDR];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
-
default:
fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]);
g_assert_not_reached();
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c1cbd03595..224f723236 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -192,10 +192,10 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
static const struct TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
- .tlb_fill = xtensa_cpu_tlb_fill,
.debug_excp_handler = xtensa_breakpoint_handler,
#ifndef CONFIG_USER_ONLY
+ .tlb_fill = xtensa_cpu_tlb_fill,
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.do_interrupt = xtensa_cpu_do_interrupt,
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f18ab383fd..29d216ec1b 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -242,27 +242,7 @@ void xtensa_cpu_list(void)
}
}
-#ifdef CONFIG_USER_ONLY
-
-bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr)
-{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
-
- qemu_log_mask(CPU_LOG_INT,
- "%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n",
- __func__, access_type, address, size);
- env->sregs[EXCVADDR] = address;
- env->sregs[EXCCAUSE] = (access_type == MMU_DATA_STORE ?
- STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE);
- cs->exception_index = EXC_USER;
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-#else /* !CONFIG_USER_ONLY */
-
+#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (39 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 40/67] target/xtensa: Make xtensa_cpu_tlb_fill " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Richard Henderson
` (25 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp, Philippe Mathieu-Daudé
We have replaced tlb_fill with record_sigsegv for user mode.
Move the declaration to restrict it to system emulation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 22 ++++++++++------------
linux-user/signal.c | 3 ---
2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 41718b695b..8eadd404c8 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -35,18 +35,6 @@ struct TCGCPUOps {
void (*cpu_exec_enter)(CPUState *cpu);
/** @cpu_exec_exit: Callback for cpu_exec cleanup */
void (*cpu_exec_exit)(CPUState *cpu);
- /**
- * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
- *
- * For system mode, if the access is valid, call tlb_set_page
- * and return true; if the access is invalid, and probe is
- * true, return false; otherwise raise an exception and do
- * not return. For user-only mode, always raise an exception
- * and do not return.
- */
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
@@ -68,6 +56,16 @@ struct TCGCPUOps {
#ifdef CONFIG_SOFTMMU
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss
+ *
+ * If the access is valid, call tlb_set_page and return true;
+ * if the access is invalid and probe is true, return false;
+ * otherwise raise an exception and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
/**
* @do_transaction_failed: Callback for handling failed memory transactions
* (ie bus faults or external aborts; not MMU faults)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 135983747d..9d60abc038 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -697,9 +697,6 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
if (tcg_ops->record_sigsegv) {
tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra);
- } else if (tcg_ops->tlb_fill) {
- tcg_ops->tlb_fill(cpu, addr, 0, access_type, MMU_USER_IDX, false, ra);
- g_assert_not_reached();
}
force_sig_fault(TARGET_SIGSEGV,
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (40 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 41/67] accel/tcg: Restrict TCGCPUOps::tlb_fill() to sysemu Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
` (24 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, alex.bennee, laurent, imp, Eduardo Habkost
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
Despite a comment saying why cpu_common_props cannot be placed in
a file that is compiled once, it was moved anyway. Revert that.
Since then, Property is not defined in hw/core/cpu.h, so it is now
easier to declare a function to install the properties rather than
the Property array itself.
Cc: Eduardo Habkost <ehabkost@redhat.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 1 +
cpu.c | 21 +++++++++++++++++++++
hw/core/cpu-common.c | 17 +----------------
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b7d5bc1200..1a10497af3 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1008,6 +1008,7 @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
/* $(top_srcdir)/cpu.c */
+void cpu_class_init_props(DeviceClass *dc);
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
diff --git a/cpu.c b/cpu.c
index e1799a15bc..9bce67ef55 100644
--- a/cpu.c
+++ b/cpu.c
@@ -179,6 +179,27 @@ void cpu_exec_unrealizefn(CPUState *cpu)
cpu_list_remove(cpu);
}
+static Property cpu_common_props[] = {
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Create a memory property for softmmu CPU object,
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
+ * because that file is compiled only once for both user-mode
+ * and system builds.) The default if no link is set up is to use
+ * the system address space.
+ */
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
+ MemoryRegion *),
+#endif
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+void cpu_class_init_props(DeviceClass *dc)
+{
+ device_class_set_props(dc, cpu_common_props);
+}
+
void cpu_exec_initfn(CPUState *cpu)
{
cpu->as = NULL;
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
index e2f5a64604..9e3241b430 100644
--- a/hw/core/cpu-common.c
+++ b/hw/core/cpu-common.c
@@ -257,21 +257,6 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
return cpu->cpu_index;
}
-static Property cpu_common_props[] = {
-#ifndef CONFIG_USER_ONLY
- /* Create a memory property for softmmu CPU object,
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
- * because that file is compiled only once for both user-mode
- * and system builds.) The default if no link is set up is to use
- * the system address space.
- */
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
- MemoryRegion *),
-#endif
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void cpu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -286,7 +271,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
dc->reset = cpu_common_reset;
- device_class_set_props(dc, cpu_common_props);
+ cpu_class_init_props(dc);
/*
* Reason: CPUs still need special care by board code: wiring up
* IRQs, adding reset handlers, halting non-first CPUs, ...
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (41 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 42/67] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:47 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
` (23 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Add a new user-only interface for updating cpu state before
raising a signal. This will take the place of do_unaligned_access
for user-only and should result in less boilerplate for each guest.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 8eadd404c8..e13898553a 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -135,6 +135,29 @@ struct TCGCPUOps {
void (*record_sigsegv)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
bool maperr, uintptr_t ra);
+ /**
+ * record_sigbus:
+ * @cpu: cpu context
+ * @addr: misaligned guest address
+ * @access_type: access was read/write/execute
+ * @ra: host pc for unwinding
+ *
+ * We are about to raise SIGBUS with si_code BUS_ADRALN,
+ * and si_addr set for @addr. Record anything further needed
+ * for the signal ucontext_t.
+ *
+ * If the emulated kernel does not provide the signal handler with
+ * anything besides the user context registers, and the siginfo_t,
+ * then this hook need do nothing and may be omitted.
+ * Otherwise, record the data and return; the caller will raise
+ * the signal, unwind the cpu state, and return to the main loop.
+ *
+ * If it is simpler to re-use the sysemu do_unaligned_access code,
+ * @ra is provided so that a "normal" cpu exception can be raised.
+ * In this case, the signal must be raised by the architecture cpu_loop.
+ */
+ void (*record_sigbus)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, uintptr_t ra);
#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus
2021-10-15 4:10 ` [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
@ 2021-10-15 18:47 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:47 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 2113 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Add a new user-only interface for updating cpu state before
> raising a signal. This will take the place of do_unaligned_access
> for user-only and should result in less boilerplate for each guest.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/tcg-cpu-ops.h | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 8eadd404c8..e13898553a 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -135,6 +135,29 @@ struct TCGCPUOps {
> void (*record_sigsegv)(CPUState *cpu, vaddr addr,
> MMUAccessType access_type,
> bool maperr, uintptr_t ra);
> + /**
> + * record_sigbus:
> + * @cpu: cpu context
> + * @addr: misaligned guest address
> + * @access_type: access was read/write/execute
> + * @ra: host pc for unwinding
> + *
> + * We are about to raise SIGBUS with si_code BUS_ADRALN,
> + * and si_addr set for @addr. Record anything further needed
> + * for the signal ucontext_t.
> + *
> + * If the emulated kernel does not provide the signal handler with
> + * anything besides the user context registers, and the siginfo_t,
> + * then this hook need do nothing and may be omitted.
> + * Otherwise, record the data and return; the caller will raise
> + * the signal, unwind the cpu state, and return to the main loop.
> + *
> + * If it is simpler to re-use the sysemu do_unaligned_access code,
> + * @ra is provided so that a "normal" cpu exception can be raised.
> + * In this case, the signal must be raised by the architecture
> cpu_loop.
> + */
> + void (*record_sigbus)(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type, uintptr_t ra);
> #endif /* CONFIG_SOFTMMU */
> #endif /* NEED_CPU_H */
>
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 3021 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (42 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 43/67] hw/core: Add TCGCPUOps.record_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 18:49 ` Warner Losh
2021-10-29 23:35 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
` (22 subsequent siblings)
66 siblings, 2 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
This is a new interface to be provided by the os emulator for
raising SIGBUS on fault. Use the new record_sigbus target hook.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 14 ++++++++++++++
linux-user/signal.c | 14 ++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f74578500c..6bb2a0f7ec 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
MMUAccessType access_type,
bool maperr, uintptr_t ra);
+/**
+ * cpu_loop_exit_sigbus:
+ * @cpu: the cpu context
+ * @addr: the guest address of the alignment fault
+ * @access_type: access was read/write/execute
+ * @ra: host pc for unwinding
+ *
+ * Use the TCGCPUOps hook to record cpu state, do guest operating system
+ * specific things to raise SIGBUS, and jump to the main cpu loop.
+ */
+void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type,
+ uintptr_t ra);
+
#else
static inline void mmap_lock(void) {}
static inline void mmap_unlock(void) {}
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 9d60abc038..df2c8678d0 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr,
cpu_loop_exit_restore(cpu, ra);
}
+void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
+ MMUAccessType access_type, uintptr_t ra)
+{
+ const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
+
+ if (tcg_ops->record_sigbus) {
+ tcg_ops->record_sigbus(cpu, addr, access_type, ra);
+ }
+
+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
+ cpu->exception_index = EXCP_INTERRUPT;
+ cpu_loop_exit_restore(cpu, ra);
+}
+
/* abort execution with signal */
static void QEMU_NORETURN dump_core_and_abort(int target_sig)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus
2021-10-15 4:10 ` [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
@ 2021-10-15 18:49 ` Warner Losh
2021-10-29 23:35 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 18:49 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 2438 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> This is a new interface to be provided by the os emulator for
> raising SIGBUS on fault. Use the new record_sigbus target hook.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 14 ++++++++++++++
> linux-user/signal.c | 14 ++++++++++++++
> 2 files changed, 28 insertions(+)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index f74578500c..6bb2a0f7ec 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -700,6 +700,20 @@ void QEMU_NORETURN cpu_loop_exit_sigsegv(CPUState
> *cpu, target_ulong addr,
> MMUAccessType access_type,
> bool maperr, uintptr_t ra);
>
> +/**
> + * cpu_loop_exit_sigbus:
> + * @cpu: the cpu context
> + * @addr: the guest address of the alignment fault
> + * @access_type: access was read/write/execute
> + * @ra: host pc for unwinding
> + *
> + * Use the TCGCPUOps hook to record cpu state, do guest operating system
> + * specific things to raise SIGBUS, and jump to the main cpu loop.
> + */
> +void QEMU_NORETURN cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
> + MMUAccessType access_type,
> + uintptr_t ra);
> +
> #else
> static inline void mmap_lock(void) {}
> static inline void mmap_unlock(void) {}
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index 9d60abc038..df2c8678d0 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -706,6 +706,20 @@ void cpu_loop_exit_sigsegv(CPUState *cpu,
> target_ulong addr,
> cpu_loop_exit_restore(cpu, ra);
> }
>
> +void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
> + MMUAccessType access_type, uintptr_t ra)
> +{
> + const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops;
> +
> + if (tcg_ops->record_sigbus) {
> + tcg_ops->record_sigbus(cpu, addr, access_type, ra);
> + }
> +
> + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
> + cpu->exception_index = EXCP_INTERRUPT;
> + cpu_loop_exit_restore(cpu, ra);
> +}
> +
> /* abort execution with signal */
> static void QEMU_NORETURN dump_core_and_abort(int target_sig)
> {
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 3366 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread* Re: [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus
2021-10-15 4:10 ` [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
2021-10-15 18:49 ` Warner Losh
@ 2021-10-29 23:35 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:35 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> This is a new interface to be provided by the os emulator for
> raising SIGBUS on fault. Use the new record_sigbus target hook.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/exec-all.h | 14 ++++++++++++++
This header deserves a system/user split.
> linux-user/signal.c | 14 ++++++++++++++
> 2 files changed, 28 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (43 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 44/67] linux-user: Add cpu_loop_exit_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
` (21 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Record trap_arg{0,1,2} for the linux-user signal frame.
Raise SIGBUS directly from cpu_loop_exit_sigbus, which means
we can remove the code for EXCP_UNALIGN in cpu_loop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.h | 8 +++++---
linux-user/alpha/cpu_loop.c | 7 -------
target/alpha/cpu.c | 1 +
target/alpha/mem_helper.c | 30 ++++++++++++++++++++++--------
4 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index d49cc36d07..afd975c878 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -282,9 +282,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
#define cpu_list alpha_cpu_list
@@ -451,10 +448,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val);
void alpha_cpu_record_sigsegv(CPUState *cs, vaddr address,
MMUAccessType access_type,
bool maperr, uintptr_t retaddr);
+void alpha_cpu_record_sigbus(CPUState *cs, vaddr address,
+ MMUAccessType access_type, uintptr_t retaddr);
#else
bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr) QEMU_NORETURN;
void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c
index 4cc8e0a55c..4029849d5c 100644
--- a/linux-user/alpha/cpu_loop.c
+++ b/linux-user/alpha/cpu_loop.c
@@ -54,13 +54,6 @@ void cpu_loop(CPUAlphaState *env)
fprintf(stderr, "External interrupt. Exit\n");
exit(EXIT_FAILURE);
break;
- case EXCP_UNALIGN:
- info.si_signo = TARGET_SIGBUS;
- info.si_errno = 0;
- info.si_code = TARGET_BUS_ADRALN;
- info._sifields._sigfault._addr = env->trap_arg0;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_OPCDEC:
do_sigill:
info.si_signo = TARGET_SIGILL;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 69f32c3078..a8990d401b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -221,6 +221,7 @@ static const struct TCGCPUOps alpha_tcg_ops = {
#ifdef CONFIG_USER_ONLY
.record_sigsegv = alpha_cpu_record_sigsegv,
+ .record_sigbus = alpha_cpu_record_sigbus,
#else
.tlb_fill = alpha_cpu_tlb_fill,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 75e72bc337..47283a0612 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -23,18 +23,12 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-/* Softmmu support */
-#ifndef CONFIG_USER_ONLY
-void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
+static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr)
{
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
uint64_t pc;
uint32_t insn;
- cpu_restore_state(cs, retaddr, true);
+ cpu_restore_state(env_cpu(env), retaddr, true);
pc = env->pc;
insn = cpu_ldl_code(env, pc);
@@ -42,6 +36,26 @@ void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->trap_arg0 = addr;
env->trap_arg1 = insn >> 26; /* opcode */
env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
+}
+
+#ifdef CONFIG_USER_ONLY
+void alpha_cpu_record_sigbus(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, uintptr_t retaddr)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
+
+ do_unaligned_access(env, addr, retaddr);
+}
+#else
+void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
+
+ do_unaligned_access(env, addr, retaddr);
cs->exception_index = EXCP_UNALIGN;
env->error_code = 0;
cpu_loop_exit(cs);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (44 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 45/67] target/alpha: Implement alpha_cpu_record_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:05 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
` (20 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Because of the complexity of setting ESR, re-use the existing
arm_cpu_do_unaligned_access function. This means we have to
handle the exception ourselves in cpu_loop, transforming it
to the appropriate signal.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 2 ++
linux-user/aarch64/cpu_loop.c | 12 +++++++++---
linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
target/arm/cpu.c | 1 +
target/arm/cpu_tcg.c | 1 +
target/arm/tlb_helper.c | 6 ++++++
6 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 5a7aaf0f51..89f7610ebc 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult result)
void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
bool maperr, uintptr_t ra);
+void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type, uintptr_t ra);
#else
bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 034b737435..97e0728b67 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -79,7 +79,7 @@
void cpu_loop(CPUARMState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr, ec, fsc, si_code;
+ int trapnr, ec, fsc, si_code, si_signo;
abi_long ret;
for (;;) {
@@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env)
fsc = extract32(env->exception.syndrome, 0, 6);
switch (fsc) {
case 0x04 ... 0x07: /* Translation fault, level {0-3} */
+ si_signo = TARGET_SIGSEGV;
si_code = TARGET_SEGV_MAPERR;
break;
case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
+ si_signo = TARGET_SIGSEGV;
si_code = TARGET_SEGV_ACCERR;
break;
case 0x11: /* Synchronous Tag Check Fault */
+ si_signo = TARGET_SIGSEGV;
si_code = TARGET_SEGV_MTESERR;
break;
+ case 0x21: /* Alignment fault */
+ si_signo = TARGET_SIGBUS;
+ si_code = TARGET_BUS_ADRALN;
+ break;
default:
g_assert_not_reached();
}
-
- force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress);
+ force_sig_fault(si_signo, si_code, env->exception.vaddress);
break;
case EXCP_DEBUG:
case EXCP_BKPT:
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index ae09adcb95..01cb6eb534 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -25,6 +25,7 @@
#include "cpu_loop-common.h"
#include "signal-common.h"
#include "semihosting/common-semi.h"
+#include "target/arm/syndrome.h"
#define get_user_code_u32(x, gaddr, env) \
({ abi_long __r = get_user_u32((x), (gaddr)); \
@@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode)
void cpu_loop(CPUARMState *env)
{
CPUState *cs = env_cpu(env);
- int trapnr;
+ int trapnr, si_signo, si_code;
unsigned int n, insn;
abi_ulong ret;
@@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- /* XXX: check env->error_code */
- force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR,
- env->exception.vaddress);
+ /* For user-only we don't set TTBCR_EAE, so look at the FSR. */
+ switch (env->exception.fsr & 0x1f) {
+ case 0x1: /* Alignment */
+ si_signo = TARGET_SIGBUS;
+ si_code = TARGET_BUS_ADRALN;
+ break;
+ case 0x3: /* Access flag fault, level 1 */
+ case 0x6: /* Access flag fault, level 2 */
+ case 0x9: /* Domain fault, level 1 */
+ case 0xb: /* Domain fault, level 2 */
+ case 0xd: /* Permision fault, level 1 */
+ case 0xf: /* Permision fault, level 2 */
+ si_signo = TARGET_SIGSEGV;
+ si_code = TARGET_SEGV_ACCERR;
+ break;
+ case 0x5: /* Translation fault, level 1 */
+ case 0x7: /* Translation fault, level 2 */
+ si_signo = TARGET_SIGSEGV;
+ si_code = TARGET_SEGV_MAPERR;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ force_sig_fault(si_signo, si_code, env->exception.vaddress);
break;
case EXCP_DEBUG:
case EXCP_BKPT:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a18a58ca0..a211804fd3 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = {
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
+ .record_sigbus = arm_cpu_record_sigbus,
#else
.tlb_fill = arm_cpu_tlb_fill,
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 7b3bea2fbb..13d0e9b195 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
+ .record_sigbus = arm_cpu_record_sigbus,
#else
.tlb_fill = arm_cpu_tlb_fill,
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index dc5860180f..12a934e924 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
cpu_restore_state(cs, ra, true);
arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
}
+
+void arm_cpu_record_sigbus(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, uintptr_t ra)
+{
+ arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra);
+}
#endif /* !defined(CONFIG_USER_ONLY) */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus
2021-10-15 4:10 ` [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
@ 2021-10-15 19:05 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 7137 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Because of the complexity of setting ESR, re-use the existing
> arm_cpu_do_unaligned_access function. This means we have to
> handle the exception ourselves in cpu_loop, transforming it
> to the appropriate signal.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/internals.h | 2 ++
> linux-user/aarch64/cpu_loop.c | 12 +++++++++---
> linux-user/arm/cpu_loop.c | 30 ++++++++++++++++++++++++++----
> target/arm/cpu.c | 1 +
> target/arm/cpu_tcg.c | 1 +
> target/arm/tlb_helper.c | 6 ++++++
> 6 files changed, 45 insertions(+), 7 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
This will definitely have an impact on the bsd-user fork, and my plans to
add arm and aarch64 to
upstream before 6.2, but I believe most of the changes will port over so
I'm not too worried.
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 5a7aaf0f51..89f7610ebc 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -548,6 +548,8 @@ static inline bool arm_extabort_type(MemTxResult
> result)
> void arm_cpu_record_sigsegv(CPUState *cpu, vaddr addr,
> MMUAccessType access_type,
> bool maperr, uintptr_t ra);
> +void arm_cpu_record_sigbus(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type, uintptr_t ra);
> #else
> bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
> index 034b737435..97e0728b67 100644
> --- a/linux-user/aarch64/cpu_loop.c
> +++ b/linux-user/aarch64/cpu_loop.c
> @@ -79,7 +79,7 @@
> void cpu_loop(CPUARMState *env)
> {
> CPUState *cs = env_cpu(env);
> - int trapnr, ec, fsc, si_code;
> + int trapnr, ec, fsc, si_code, si_signo;
> abi_long ret;
>
> for (;;) {
> @@ -121,20 +121,26 @@ void cpu_loop(CPUARMState *env)
> fsc = extract32(env->exception.syndrome, 0, 6);
> switch (fsc) {
> case 0x04 ... 0x07: /* Translation fault, level {0-3} */
> + si_signo = TARGET_SIGSEGV;
> si_code = TARGET_SEGV_MAPERR;
> break;
> case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
> case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
> + si_signo = TARGET_SIGSEGV;
> si_code = TARGET_SEGV_ACCERR;
> break;
> case 0x11: /* Synchronous Tag Check Fault */
> + si_signo = TARGET_SIGSEGV;
> si_code = TARGET_SEGV_MTESERR;
> break;
> + case 0x21: /* Alignment fault */
> + si_signo = TARGET_SIGBUS;
> + si_code = TARGET_BUS_ADRALN;
> + break;
> default:
> g_assert_not_reached();
> }
> -
> - force_sig_fault(TARGET_SIGSEGV, si_code,
> env->exception.vaddress);
> + force_sig_fault(si_signo, si_code, env->exception.vaddress);
> break;
> case EXCP_DEBUG:
> case EXCP_BKPT:
> diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
> index ae09adcb95..01cb6eb534 100644
> --- a/linux-user/arm/cpu_loop.c
> +++ b/linux-user/arm/cpu_loop.c
> @@ -25,6 +25,7 @@
> #include "cpu_loop-common.h"
> #include "signal-common.h"
> #include "semihosting/common-semi.h"
> +#include "target/arm/syndrome.h"
>
> #define get_user_code_u32(x, gaddr, env) \
> ({ abi_long __r = get_user_u32((x), (gaddr)); \
> @@ -280,7 +281,7 @@ static bool emulate_arm_fpa11(CPUARMState *env,
> uint32_t opcode)
> void cpu_loop(CPUARMState *env)
> {
> CPUState *cs = env_cpu(env);
> - int trapnr;
> + int trapnr, si_signo, si_code;
> unsigned int n, insn;
> abi_ulong ret;
>
> @@ -423,9 +424,30 @@ void cpu_loop(CPUARMState *env)
> break;
> case EXCP_PREFETCH_ABORT:
> case EXCP_DATA_ABORT:
> - /* XXX: check env->error_code */
> - force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MAPERR,
> - env->exception.vaddress);
> + /* For user-only we don't set TTBCR_EAE, so look at the FSR.
> */
> + switch (env->exception.fsr & 0x1f) {
> + case 0x1: /* Alignment */
> + si_signo = TARGET_SIGBUS;
> + si_code = TARGET_BUS_ADRALN;
> + break;
> + case 0x3: /* Access flag fault, level 1 */
> + case 0x6: /* Access flag fault, level 2 */
> + case 0x9: /* Domain fault, level 1 */
> + case 0xb: /* Domain fault, level 2 */
> + case 0xd: /* Permision fault, level 1 */
> + case 0xf: /* Permision fault, level 2 */
> + si_signo = TARGET_SIGSEGV;
> + si_code = TARGET_SEGV_ACCERR;
> + break;
> + case 0x5: /* Translation fault, level 1 */
> + case 0x7: /* Translation fault, level 2 */
> + si_signo = TARGET_SIGSEGV;
> + si_code = TARGET_SEGV_MAPERR;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + force_sig_fault(si_signo, si_code, env->exception.vaddress);
> break;
> case EXCP_DEBUG:
> case EXCP_BKPT:
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 7a18a58ca0..a211804fd3 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2035,6 +2035,7 @@ static const struct TCGCPUOps arm_tcg_ops = {
>
> #ifdef CONFIG_USER_ONLY
> .record_sigsegv = arm_cpu_record_sigsegv,
> + .record_sigbus = arm_cpu_record_sigbus,
> #else
> .tlb_fill = arm_cpu_tlb_fill,
> .cpu_exec_interrupt = arm_cpu_exec_interrupt,
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 7b3bea2fbb..13d0e9b195 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
>
> #ifdef CONFIG_USER_ONLY
> .record_sigsegv = arm_cpu_record_sigsegv,
> + .record_sigbus = arm_cpu_record_sigbus,
> #else
> .tlb_fill = arm_cpu_tlb_fill,
> .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
> diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> index dc5860180f..12a934e924 100644
> --- a/target/arm/tlb_helper.c
> +++ b/target/arm/tlb_helper.c
> @@ -213,4 +213,10 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr,
> cpu_restore_state(cs, ra, true);
> arm_deliver_fault(cpu, addr, access_type, MMU_USER_IDX, &fi);
> }
> +
> +void arm_cpu_record_sigbus(CPUState *cs, vaddr addr,
> + MMUAccessType access_type, uintptr_t ra)
> +{
> + arm_cpu_do_unaligned_access(cs, addr, access_type, MMU_USER_IDX, ra);
> +}
> #endif /* !defined(CONFIG_USER_ONLY) */
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 8958 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (45 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 46/67] target/arm: Implement arm_cpu_record_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
` (19 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/cpu_loop.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index e0a62deeb9..375576c8f0 100644
--- a/linux-user/hppa/cpu_loop.c
+++ b/linux-user/hppa/cpu_loop.c
@@ -144,13 +144,6 @@ void cpu_loop(CPUHPPAState *env)
env->iaoq_f = env->gr[31];
env->iaoq_b = env->gr[31] + 4;
break;
- case EXCP_UNALIGN:
- info.si_signo = TARGET_SIGBUS;
- info.si_errno = 0;
- info.si_code = 0;
- info._sifields._sigfault._addr = env->cr[CR_IOR];
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case EXCP_ILL:
case EXCP_PRIV_OPR:
case EXCP_PRIV_REG:
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (46 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 47/67] linux-user/hppa: Remove EXCP_UNALIGN handling Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
` (18 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E . Iglesias, alex.bennee, laurent, imp
The kernel will fix up unaligned accesses, so emulate that
by allowing unaligned accesses to succeed.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index a14ffed784..ef44bca2fd 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -727,6 +727,7 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
}
#endif
+#ifndef CONFIG_USER_ONLY
static void record_unaligned_ess(DisasContext *dc, int rd,
MemOp size, bool store)
{
@@ -739,6 +740,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
tcg_set_insn_start_param(dc->insn_start, 1, iflags);
}
+#endif
static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
int mem_index, bool rev)
@@ -760,12 +762,19 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, false);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);
@@ -906,12 +915,19 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr, MemOp mop,
}
}
+ /*
+ * For system mode, enforce alignment if the cpu configuration
+ * requires it. For user-mode, the Linux kernel will have fixed up
+ * any unaligned access, so emulate that by *not* setting MO_ALIGN.
+ */
+#ifndef CONFIG_USER_ONLY
if (size > MO_8 &&
(dc->tb_flags & MSR_EE) &&
dc->cfg->unaligned_exceptions) {
record_unaligned_ess(dc, rd, size, true);
mop |= MO_ALIGN;
}
+#endif
tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (47 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 48/67] target/microblaze: Do not set MO_ALIGN for user-only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
` (17 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, alex.bennee, laurent, imp
By doing this while sending the exception, we will have already
done the unwinding, which makes the ppc_cpu_do_unaligned_access
code a bit cleaner.
Update the comment about the expected instruction format.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/excp_helper.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b7d1767920..88a8de4b80 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -454,13 +454,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
break;
}
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* Get rS/rD and rA from faulting opcode */
/*
- * Note: the opcode fields will not be set properly for a
- * direct store load/store, but nobody cares as nobody
- * actually uses direct store segments.
+ * Get rS/rD and rA from faulting opcode.
+ * Note: We will only invoke ALIGN for atomic operations,
+ * so all instructions are X-form.
*/
- env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
+ {
+ uint32_t insn = cpu_ldl_code(env, env->nip);
+ env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16;
+ }
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
@@ -1462,14 +1464,9 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
int mmu_idx, uintptr_t retaddr)
{
CPUPPCState *env = cs->env_ptr;
- uint32_t insn;
-
- /* Restore state and reload the insn we executed, for filling in DSISR. */
- cpu_restore_state(cs, retaddr, true);
- insn = cpu_ldl_code(env, env->nip);
cs->exception_index = POWERPC_EXCP_ALIGN;
- env->error_code = insn & 0x03FF0000;
- cpu_loop_exit(cs);
+ env->error_code = 0;
+ cpu_loop_exit_restore(cs, retaddr);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (48 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 49/67] target/ppc: Move SPR_DSISR setting to powerpc_excp Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
` (16 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, alex.bennee, laurent, imp, Peter Maydell
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: qemu-ppc@nongnu.org
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/excp_helper.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 88a8de4b80..e568a54536 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1465,6 +1465,20 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
{
CPUPPCState *env = cs->env_ptr;
+ switch (env->mmu_model) {
+ case POWERPC_MMU_SOFT_4xx:
+ case POWERPC_MMU_SOFT_4xx_Z:
+ env->spr[SPR_40x_DEAR] = vaddr;
+ break;
+ case POWERPC_MMU_BOOKE:
+ case POWERPC_MMU_BOOKE206:
+ env->spr[SPR_BOOKE_DEAR] = vaddr;
+ break;
+ default:
+ env->spr[SPR_DAR] = vaddr;
+ break;
+ }
+
cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = 0;
cpu_loop_exit_restore(cs, retaddr);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (49 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 50/67] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:06 ` Warner Losh
2021-10-29 23:36 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
` (15 subsequent siblings)
66 siblings, 2 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
This is not used by, nor required by, user-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/internal.h | 8 +++-----
target/ppc/excp_helper.c | 8 +++-----
2 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 339974b7d8..6aa9484f34 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
-/* Raise a data fault alignment exception for the specified virtual address */
-void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
-
/* translate.c */
int ppc_fixup_cpu(PowerPCCPU *cpu);
@@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr) QEMU_NORETURN;
#endif
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e568a54536..17607adbe4 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
}
-#endif
-#endif /* CONFIG_TCG */
-#endif
+#endif /* TARGET_PPC64 */
-#ifdef CONFIG_TCG
void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
env->error_code = 0;
cpu_loop_exit_restore(cs, retaddr);
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
2021-10-15 4:10 ` [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
@ 2021-10-15 19:06 ` Warner Losh
2021-10-29 23:36 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:06 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 2528 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> This is not used by, nor required by, user-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/ppc/internal.h | 8 +++-----
> target/ppc/excp_helper.c | 8 +++-----
> 2 files changed, 6 insertions(+), 10 deletions(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/target/ppc/internal.h b/target/ppc/internal.h
> index 339974b7d8..6aa9484f34 100644
> --- a/target/ppc/internal.h
> +++ b/target/ppc/internal.h
> @@ -211,11 +211,6 @@ void helper_compute_fprf_float16(CPUPPCState *env,
> float16 arg);
> void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
> void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
>
> -/* Raise a data fault alignment exception for the specified virtual
> address */
> -void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type, int mmu_idx,
> - uintptr_t retaddr) QEMU_NORETURN;
> -
> /* translate.c */
>
> int ppc_fixup_cpu(PowerPCCPU *cpu);
> @@ -291,6 +286,9 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
> bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> +void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> + MMUAccessType access_type, int mmu_idx,
> + uintptr_t retaddr) QEMU_NORETURN;
> #endif
>
> #endif /* PPC_INTERNAL_H */
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index e568a54536..17607adbe4 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1454,11 +1454,8 @@ void helper_book3s_msgsndp(CPUPPCState *env,
> target_ulong rb)
>
> book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
> }
> -#endif
> -#endif /* CONFIG_TCG */
> -#endif
> +#endif /* TARGET_PPC64 */
>
> -#ifdef CONFIG_TCG
> void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> @@ -1483,4 +1480,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
> vaddr,
> env->error_code = 0;
> cpu_loop_exit_restore(cs, retaddr);
> }
> -#endif
> +#endif /* CONFIG_TCG */
> +#endif /* !CONFIG_USER_ONLY */
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 3468 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* Re: [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
2021-10-15 4:10 ` [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
2021-10-15 19:06 ` Warner Losh
@ 2021-10-29 23:36 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:36 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> This is not used by, nor required by, user-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/ppc/internal.h | 8 +++-----
> target/ppc/excp_helper.c | 8 +++-----
> 2 files changed, 6 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (50 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 51/67] target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-29 23:38 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
` (14 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
For s390x, the only unaligned accesses that are signaled are atomic,
and we don't actually want to raise SIGBUS for those, but instead
raise a SPECIFICATION error, which the kernel will report as SIGILL.
Split out a do_unaligned_access function to share between the user-only
s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/s390x-internal.h | 8 +++++---
target/s390x/cpu.c | 1 +
target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++-------
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 163aa4f94a..1a178aed41 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
void s390x_cpu_debug_excp_handler(CPUState *cs);
void s390_cpu_do_interrupt(CPUState *cpu);
bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type, int mmu_idx,
- uintptr_t retaddr) QEMU_NORETURN;
#ifdef CONFIG_USER_ONLY
void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
MMUAccessType access_type,
bool maperr, uintptr_t retaddr);
+void s390_cpu_record_sigbus(CPUState *cs, vaddr address,
+ MMUAccessType access_type, uintptr_t retaddr);
#else
bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type, int mmu_idx,
+ uintptr_t retaddr) QEMU_NORETURN;
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 593dda75c4..ccdbaf84d5 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops = {
#ifdef CONFIG_USER_ONLY
.record_sigsegv = s390_cpu_record_sigsegv,
+ .record_sigbus = s390_cpu_record_sigbus,
#else
.tlb_fill = s390_cpu_tlb_fill,
.cpu_exec_interrupt = s390_cpu_exec_interrupt,
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index b923d080fc..4e7648f301 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
tcg_s390_data_exception(env, dxc, GETPC());
}
+/*
+ * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
+ * this is only for the atomic operations, for which we want to raise a
+ * specification exception.
+ */
+static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr)
+{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
+ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
+}
+
#if defined(CONFIG_USER_ONLY)
void s390_cpu_do_interrupt(CPUState *cs)
@@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
cpu_loop_exit_restore(cs, retaddr);
}
+void s390_cpu_record_sigbus(CPUState *cs, vaddr address,
+ MMUAccessType access_type, uintptr_t retaddr)
+{
+ do_unaligned_access(cs, retaddr);
+}
+
#else /* !CONFIG_USER_ONLY */
static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
@@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs)
}
}
-/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
- this is only for the atomic operations, for which we want to raise a
- specification exception. */
void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
- S390CPU *cpu = S390_CPU(cs);
- CPUS390XState *env = &cpu->env;
-
- tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
+ do_unaligned_access(cs, retaddr);
}
static void QEMU_NORETURN monitor_event(CPUS390XState *env,
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus
2021-10-15 4:10 ` [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
@ 2021-10-29 23:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x, alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> For s390x, the only unaligned accesses that are signaled are atomic,
> and we don't actually want to raise SIGBUS for those, but instead
> raise a SPECIFICATION error, which the kernel will report as SIGILL.
>
> Split out a do_unaligned_access function to share between the user-only
> s390x_cpu_record_sigbus and the sysemu s390x_do_unaligned_access.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/s390x/s390x-internal.h | 8 +++++---
> target/s390x/cpu.c | 1 +
> target/s390x/tcg/excp_helper.c | 27 ++++++++++++++++++++-------
> 3 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
> index 163aa4f94a..1a178aed41 100644
> --- a/target/s390x/s390x-internal.h
> +++ b/target/s390x/s390x-internal.h
> @@ -270,18 +270,20 @@ ObjectClass *s390_cpu_class_by_name(const char *name);
> void s390x_cpu_debug_excp_handler(CPUState *cs);
> void s390_cpu_do_interrupt(CPUState *cpu);
> bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
> -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type, int mmu_idx,
> - uintptr_t retaddr) QEMU_NORETURN;
>
> #ifdef CONFIG_USER_ONLY
> void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
> MMUAccessType access_type,
> bool maperr, uintptr_t retaddr);
> +void s390_cpu_record_sigbus(CPUState *cs, vaddr address,
> + MMUAccessType access_type, uintptr_t retaddr);
> #else
> bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> + MMUAccessType access_type, int mmu_idx,
> + uintptr_t retaddr) QEMU_NORETURN;
> #endif
>
>
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index 593dda75c4..ccdbaf84d5 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -269,6 +269,7 @@ static const struct TCGCPUOps s390_tcg_ops = {
>
> #ifdef CONFIG_USER_ONLY
> .record_sigsegv = s390_cpu_record_sigsegv,
> + .record_sigbus = s390_cpu_record_sigbus,
> #else
> .tlb_fill = s390_cpu_tlb_fill,
> .cpu_exec_interrupt = s390_cpu_exec_interrupt,
> diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
> index b923d080fc..4e7648f301 100644
> --- a/target/s390x/tcg/excp_helper.c
> +++ b/target/s390x/tcg/excp_helper.c
> @@ -82,6 +82,19 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
> tcg_s390_data_exception(env, dxc, GETPC());
> }
>
> +/*
> + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
> + * this is only for the atomic operations, for which we want to raise a
> + * specification exception.
> + */
> +static void QEMU_NORETURN do_unaligned_access(CPUState *cs, uintptr_t retaddr)
> +{
> + S390CPU *cpu = S390_CPU(cs);
> + CPUS390XState *env = &cpu->env;
> +
> + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
> +}
> +
> #if defined(CONFIG_USER_ONLY)
>
> void s390_cpu_do_interrupt(CPUState *cs)
> @@ -106,6 +119,12 @@ void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
> cpu_loop_exit_restore(cs, retaddr);
> }
>
> +void s390_cpu_record_sigbus(CPUState *cs, vaddr address,
> + MMUAccessType access_type, uintptr_t retaddr)
> +{
> + do_unaligned_access(cs, retaddr);
> +}
> +
> #else /* !CONFIG_USER_ONLY */
>
> static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
> @@ -593,17 +612,11 @@ void s390x_cpu_debug_excp_handler(CPUState *cs)
> }
> }
>
> -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
> - this is only for the atomic operations, for which we want to raise a
> - specification exception. */
> void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> - S390CPU *cpu = S390_CPU(cs);
> - CPUS390XState *env = &cpu->env;
> -
> - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
> + do_unaligned_access(cs, retaddr);
> }
>
> static void QEMU_NORETURN monitor_event(CPUS390XState *env,
>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (51 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 52/67] target/s390x: Implement s390x_cpu_record_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-29 23:39 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
` (13 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
We will raise SIGBUS directly from cpu_loop_exit_sigbus.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/ppc/cpu_loop.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index 840b23736b..483e669300 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env)
cpu_abort(cs, "External interrupt while in user mode. "
"Aborting\n");
break;
- case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* XXX: check this */
- info.si_signo = TARGET_SIGBUS;
- info.si_errno = 0;
- info.si_code = TARGET_BUS_ADRALN;
- info._sifields._sigfault._addr = env->nip;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
- break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
case POWERPC_EXCP_HV_EMU: /* HV emulation */
/* XXX: check this */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling
2021-10-15 4:10 ` [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
@ 2021-10-29 23:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
Typo s/hppa/ppc/ in subject.
On 10/15/21 06:10, Richard Henderson wrote:
> We will raise SIGBUS directly from cpu_loop_exit_sigbus.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/ppc/cpu_loop.c | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
> index 840b23736b..483e669300 100644
> --- a/linux-user/ppc/cpu_loop.c
> +++ b/linux-user/ppc/cpu_loop.c
> @@ -162,14 +162,6 @@ void cpu_loop(CPUPPCState *env)
> cpu_abort(cs, "External interrupt while in user mode. "
> "Aborting\n");
> break;
> - case POWERPC_EXCP_ALIGN: /* Alignment exception */
> - /* XXX: check this */
> - info.si_signo = TARGET_SIGBUS;
> - info.si_errno = 0;
> - info.si_code = TARGET_BUS_ADRALN;
> - info._sifields._sigfault._addr = env->nip;
> - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> - break;
> case POWERPC_EXCP_PROGRAM: /* Program exception */
> case POWERPC_EXCP_HV_EMU: /* HV emulation */
> /* XXX: check this */
>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (52 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 53/67] linux-user/hppa: Remove POWERPC_EXCP_ALIGN handling Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
` (12 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, alex.bennee, laurent, imp,
Yoshinori Sato
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/op_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index c0cbb95382..d6d70c339f 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
+ CPUSH4State *env = cs->env_ptr;
+
+ env->tea = addr;
switch (access_type) {
case MMU_INST_FETCH:
case MMU_DATA_LOAD:
@@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
case MMU_DATA_STORE:
cs->exception_index = 0x100;
break;
+ default:
+ g_assert_not_reached();
}
cpu_loop_exit_restore(cs, retaddr);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (53 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 54/67] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 56/67] target/sparc: Split out build_sfsr Richard Henderson
` (11 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel
Cc: Mark Cave-Ayland, alex.bennee, laurent, imp,
Philippe Mathieu-Daudé
The printf should have been qemu_log_mask, the parameters
themselves no longer compile, and because this is placed
before unwinding the PC is actively wrong.
We get better (and correct) logging on the other side of
raising the exception, in sparc_cpu_do_interrupt.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index bbf3601cb1..0549b6adf1 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -27,7 +27,6 @@
//#define DEBUG_MMU
//#define DEBUG_MXCC
-//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
//#define DEBUG_ASI
//#define DEBUG_CACHE_CONTROL
@@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr,
uint32_t align, uintptr_t ra)
{
if (addr & align) {
-#ifdef DEBUG_UNALIGNED
- printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
- "\n", addr, env->pc);
-#endif
cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
}
}
@@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
-#ifdef DEBUG_UNALIGNED
- printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
- "\n", addr, env->pc);
-#endif
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 56/67] target/sparc: Split out build_sfsr
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (54 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 55/67] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
` (10 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland, alex.bennee, laurent, imp
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/mmu_helper.c | 72 +++++++++++++++++++++++++--------------
1 file changed, 46 insertions(+), 26 deletions(-)
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 2ad47391d0..014601e701 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -502,16 +502,60 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
return 0;
}
+static uint64_t build_sfsr(CPUSPARCState *env, int mmu_idx, int rw)
+{
+ uint64_t sfsr = SFSR_VALID_BIT;
+
+ switch (mmu_idx) {
+ case MMU_PHYS_IDX:
+ sfsr |= SFSR_CT_NOTRANS;
+ break;
+ case MMU_USER_IDX:
+ case MMU_KERNEL_IDX:
+ sfsr |= SFSR_CT_PRIMARY;
+ break;
+ case MMU_USER_SECONDARY_IDX:
+ case MMU_KERNEL_SECONDARY_IDX:
+ sfsr |= SFSR_CT_SECONDARY;
+ break;
+ case MMU_NUCLEUS_IDX:
+ sfsr |= SFSR_CT_NUCLEUS;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (rw == 1) {
+ sfsr |= SFSR_WRITE_BIT;
+ } else if (rw == 4) {
+ sfsr |= SFSR_NF_BIT;
+ }
+
+ if (env->pstate & PS_PRIV) {
+ sfsr |= SFSR_PR_BIT;
+ }
+
+ if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
+ sfsr |= SFSR_OW_BIT; /* overflow (not read before another fault) */
+ }
+
+ /* FIXME: ASI field in SFSR must be set */
+
+ return sfsr;
+}
+
static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
int *prot, MemTxAttrs *attrs,
target_ulong address, int rw, int mmu_idx)
{
CPUState *cs = env_cpu(env);
unsigned int i;
+ uint64_t sfsr;
uint64_t context;
- uint64_t sfsr = 0;
bool is_user = false;
+ sfsr = build_sfsr(env, mmu_idx, rw);
+
switch (mmu_idx) {
case MMU_PHYS_IDX:
g_assert_not_reached();
@@ -520,29 +564,18 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
/* fallthru */
case MMU_KERNEL_IDX:
context = env->dmmu.mmu_primary_context & 0x1fff;
- sfsr |= SFSR_CT_PRIMARY;
break;
case MMU_USER_SECONDARY_IDX:
is_user = true;
/* fallthru */
case MMU_KERNEL_SECONDARY_IDX:
context = env->dmmu.mmu_secondary_context & 0x1fff;
- sfsr |= SFSR_CT_SECONDARY;
break;
- case MMU_NUCLEUS_IDX:
- sfsr |= SFSR_CT_NUCLEUS;
- /* FALLTHRU */
default:
context = 0;
break;
}
- if (rw == 1) {
- sfsr |= SFSR_WRITE_BIT;
- } else if (rw == 4) {
- sfsr |= SFSR_NF_BIT;
- }
-
for (i = 0; i < 64; i++) {
/* ctx match, vaddr match, valid? */
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
@@ -592,22 +625,9 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical,
return 0;
}
- if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
- sfsr |= SFSR_OW_BIT; /* overflow (not read before
- another fault) */
- }
-
- if (env->pstate & PS_PRIV) {
- sfsr |= SFSR_PR_BIT;
- }
-
- /* FIXME: ASI field in SFSR must be set */
- env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
-
+ env->dmmu.sfsr = sfsr;
env->dmmu.sfar = address; /* Fault address register */
-
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
-
return 1;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (55 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 56/67] target/sparc: Split out build_sfsr Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Richard Henderson
` (9 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland, alex.bennee, laurent, imp
We ought to have been recording the virtual address for reporting
to the guest trap handler. Move the function to mmu_helper.c, so
that we can re-use code shared with get_physical_address_data.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 13 -------------
target/sparc/mmu_helper.c | 20 ++++++++++++++++++++
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 0549b6adf1..a3e1cf9b6e 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1953,16 +1953,3 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
is_asi, size, retaddr);
}
#endif
-
-#if !defined(CONFIG_USER_ONLY)
-void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx,
- uintptr_t retaddr)
-{
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
- cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
-}
-#endif
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 014601e701..f2668389b0 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -922,3 +922,23 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
return phys_addr;
}
+
+#ifndef CONFIG_USER_ONLY
+void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx,
+ uintptr_t retaddr)
+{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
+#ifdef TARGET_SPARC64
+ env->dmmu.sfsr = build_sfsr(env, mmu_idx, access_type);
+ env->dmmu.sfar = addr;
+#else
+ env->mmuregs[4] = addr;
+#endif
+
+ cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
+}
+#endif /* !CONFIG_USER_ONLY */
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (56 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 57/67] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:08 ` Warner Losh
2021-10-29 23:43 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 59/67] accel/tcg: Report unaligned load/store " Richard Henderson
` (8 subsequent siblings)
66 siblings, 2 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
has access to complete alignment info from the TCGMemOpIdx arg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5646f8e527..92cbffd7c6 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
MemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
+ MemOp mop = get_memop(oi);
+ int a_bits = get_alignment_bits(mop);
+ void *ret;
+
+ /* Enforce guest required alignment. */
+ if (unlikely(addr & ((1 << a_bits) - 1))) {
+ MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE;
+ cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr);
+ }
+
/* Enforce qemu required alignment. */
if (unlikely(addr & (size - 1))) {
cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
- void *ret = g2h(env_cpu(env), addr);
+
+ ret = g2h(env_cpu(env), addr);
set_helper_retaddr(retaddr);
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only
2021-10-15 4:10 ` [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Richard Henderson
@ 2021-10-15 19:08 ` Warner Losh
2021-10-29 23:43 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 1600 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
> has access to complete alignment info from the TCGMemOpIdx arg.
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/user-exec.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 5646f8e527..92cbffd7c6 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env,
> target_ulong addr,
> MemOpIdx oi, int size, int prot,
> uintptr_t retaddr)
> {
> + MemOp mop = get_memop(oi);
> + int a_bits = get_alignment_bits(mop);
> + void *ret;
> +
> + /* Enforce guest required alignment. */
> + if (unlikely(addr & ((1 << a_bits) - 1))) {
> + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD :
> MMU_DATA_STORE;
> + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr);
> + }
> +
> /* Enforce qemu required alignment. */
> if (unlikely(addr & (size - 1))) {
> cpu_loop_exit_atomic(env_cpu(env), retaddr);
> }
> - void *ret = g2h(env_cpu(env), addr);
> +
> + ret = g2h(env_cpu(env), addr);
> set_helper_retaddr(retaddr);
> return ret;
> }
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 2445 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread* Re: [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only
2021-10-15 4:10 ` [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Richard Henderson
2021-10-15 19:08 ` Warner Losh
@ 2021-10-29 23:43 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> Use the new cpu_loop_exit_sigbus for atomic_mmu_lookup, which
> has access to complete alignment info from the TCGMemOpIdx arg.
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/user-exec.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 5646f8e527..92cbffd7c6 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -476,11 +476,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
> MemOpIdx oi, int size, int prot,
> uintptr_t retaddr)
> {
> + MemOp mop = get_memop(oi);
> + int a_bits = get_alignment_bits(mop);
> + void *ret;
> +
> + /* Enforce guest required alignment. */
> + if (unlikely(addr & ((1 << a_bits) - 1))) {
QEMU_IS_ALIGNED(addr, 1 << a_bits) ?
> + MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE;
> + cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr);
> + }
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 59/67] accel/tcg: Report unaligned load/store for user-only
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (57 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 58/67] accel/tcg: Report unaligned atomics for user-only Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:08 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
` (7 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, alex.bennee, laurent, imp
Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 92cbffd7c6..7d50dd54f6 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -220,9 +220,14 @@ static void validate_memop(MemOpIdx oi, MemOp expected)
static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t ra, MMUAccessType type)
{
+ MemOp mop = get_memop(oi);
+ int a_bits = get_alignment_bits(mop);
void *ret;
- /* TODO: Enforce guest required alignment. */
+ /* Enforce guest required alignment. */
+ if (unlikely(addr & ((1 << a_bits) - 1))) {
+ cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra);
+ }
ret = g2h(env_cpu(env), addr);
set_helper_retaddr(ra);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 59/67] accel/tcg: Report unaligned load/store for user-only
2021-10-15 4:10 ` [PATCH v5 59/67] accel/tcg: Report unaligned load/store " Richard Henderson
@ 2021-10-15 19:08 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:08 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 1216 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> Use the new cpu_loop_exit_sigbus for cpu_mmu_lookup.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/user-exec.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 92cbffd7c6..7d50dd54f6 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -220,9 +220,14 @@ static void validate_memop(MemOpIdx oi, MemOp
> expected)
> static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
> MemOpIdx oi, uintptr_t ra, MMUAccessType type)
> {
> + MemOp mop = get_memop(oi);
> + int a_bits = get_alignment_bits(mop);
> void *ret;
>
> - /* TODO: Enforce guest required alignment. */
> + /* Enforce guest required alignment. */
> + if (unlikely(addr & ((1 << a_bits) - 1))) {
> + cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra);
> + }
>
> ret = g2h(env_cpu(env), addr);
> set_helper_retaddr(ra);
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 2051 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (58 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 59/67] accel/tcg: Report unaligned load/store " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:09 ` Warner Losh
2021-10-29 23:44 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
` (6 subsequent siblings)
66 siblings, 2 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, alex.bennee, laurent, imp
To be called from tcg generated code on hosts that support
unaligned accesses natively, in response to an access that
is supposed to be aligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-ldst.h | 5 +++++
accel/tcg/user-exec.c | 11 +++++++++++
2 files changed, 16 insertions(+)
diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h
index 8c86365611..bf40942de4 100644
--- a/include/tcg/tcg-ldst.h
+++ b/include/tcg/tcg-ldst.h
@@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
MemOpIdx oi, uintptr_t retaddr);
+#else
+
+void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong addr);
+void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong addr);
+
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_LDST_H */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 7d50dd54f6..0473ead5ab 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -27,6 +27,7 @@
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "trace/trace-root.h"
+#include "tcg/tcg-ldst.h"
#include "internal.h"
__thread uintptr_t helper_retaddr;
@@ -217,6 +218,16 @@ static void validate_memop(MemOpIdx oi, MemOp expected)
#endif
}
+void helper_unaligned_ld(CPUArchState *env, target_ulong addr)
+{
+ cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC());
+}
+
+void helper_unaligned_st(CPUArchState *env, target_ulong addr)
+{
+ cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC());
+}
+
static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t ra, MMUAccessType type)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus
2021-10-15 4:10 ` [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
@ 2021-10-15 19:09 ` Warner Losh
2021-10-29 23:44 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:09 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 2124 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> To be called from tcg generated code on hosts that support
> unaligned accesses natively, in response to an access that
> is supposed to be aligned.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-ldst.h | 5 +++++
> accel/tcg/user-exec.c | 11 +++++++++++
> 2 files changed, 16 insertions(+)
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h
> index 8c86365611..bf40942de4 100644
> --- a/include/tcg/tcg-ldst.h
> +++ b/include/tcg/tcg-ldst.h
> @@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong
> addr, uint32_t val,
> void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
> MemOpIdx oi, uintptr_t retaddr);
>
> +#else
> +
> +void QEMU_NORETURN helper_unaligned_ld(CPUArchState *env, target_ulong
> addr);
> +void QEMU_NORETURN helper_unaligned_st(CPUArchState *env, target_ulong
> addr);
> +
> #endif /* CONFIG_SOFTMMU */
> #endif /* TCG_LDST_H */
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 7d50dd54f6..0473ead5ab 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -27,6 +27,7 @@
> #include "exec/helper-proto.h"
> #include "qemu/atomic128.h"
> #include "trace/trace-root.h"
> +#include "tcg/tcg-ldst.h"
> #include "internal.h"
>
> __thread uintptr_t helper_retaddr;
> @@ -217,6 +218,16 @@ static void validate_memop(MemOpIdx oi, MemOp
> expected)
> #endif
> }
>
> +void helper_unaligned_ld(CPUArchState *env, target_ulong addr)
> +{
> + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_LOAD, GETPC());
> +}
> +
> +void helper_unaligned_st(CPUArchState *env, target_ulong addr)
> +{
> + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, GETPC());
> +}
> +
> static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
> MemOpIdx oi, uintptr_t ra, MMUAccessType type)
> {
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 3077 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread* Re: [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus
2021-10-15 4:10 ` [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
2021-10-15 19:09 ` Warner Losh
@ 2021-10-29 23:44 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Peter Maydell, alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> To be called from tcg generated code on hosts that support
> unaligned accesses natively, in response to an access that
> is supposed to be aligned.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-ldst.h | 5 +++++
> accel/tcg/user-exec.c | 11 +++++++++++
> 2 files changed, 16 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (59 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 60/67] tcg: Add helper_unaligned_{ld, st} for user-only sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-29 23:46 ` Philippe Mathieu-Daudé
2021-10-15 4:10 ` [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines Richard Henderson
` (5 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS
si_codes to continue into the host-to-guest signal coversion code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index df2c8678d0..81c45bfce9 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
} else {
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
+ if (info->si_code == BUS_ADRALN) {
+ cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc);
+ }
}
sync_sig = true;
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler
2021-10-15 4:10 ` [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
@ 2021-10-29 23:46 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 101+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-29 23:46 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: alex.bennee, laurent, imp
On 10/15/21 06:10, Richard Henderson wrote:
> Handle BUS_ADRALN via cpu_loop_exit_sigbus, but allow other SIGBUS
> si_codes to continue into the host-to-guest signal coversion code.
Typo "conversion".
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/signal.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index df2c8678d0..81c45bfce9 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -860,6 +860,9 @@ static void host_signal_handler(int host_sig, siginfo_t *info, void *puc)
> cpu_loop_exit_sigsegv(cpu, guest_addr, access_type, maperr, pc);
> } else {
> sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
> + if (info->si_code == BUS_ADRALN) {
> + cpu_loop_exit_sigbus(cpu, guest_addr, access_type, pc);
> + }
> }
To the best of my knowledge,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (60 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 61/67] linux-user: Handle BUS_ADRALN in host_signal_handler Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 63/67] linux-user: Disable more prctl subcodes Richard Henderson
` (4 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Since the prctl constants are supposed to be generic, supply
any that are not provided by the host.
Split out subroutines for PR_GET_FP_MODE, PR_SET_FP_MODE,
PR_GET_VL, PR_SET_VL, PR_RESET_KEYS, PR_SET_TAGGED_ADDR_CTRL,
PR_GET_TAGGED_ADDR_CTRL. Return EINVAL for guests that do
not support these options rather than pass them on to the host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/target_prctl.h | 160 ++++++++++
linux-user/aarch64/target_syscall.h | 23 --
linux-user/alpha/target_prctl.h | 1 +
linux-user/arm/target_prctl.h | 1 +
linux-user/cris/target_prctl.h | 1 +
linux-user/hexagon/target_prctl.h | 1 +
linux-user/hppa/target_prctl.h | 1 +
linux-user/i386/target_prctl.h | 1 +
linux-user/m68k/target_prctl.h | 1 +
linux-user/microblaze/target_prctl.h | 1 +
linux-user/mips/target_prctl.h | 88 ++++++
linux-user/mips/target_syscall.h | 6 -
linux-user/mips64/target_prctl.h | 1 +
linux-user/mips64/target_syscall.h | 6 -
linux-user/nios2/target_prctl.h | 1 +
linux-user/openrisc/target_prctl.h | 1 +
linux-user/ppc/target_prctl.h | 1 +
linux-user/riscv/target_prctl.h | 1 +
linux-user/s390x/target_prctl.h | 1 +
linux-user/sh4/target_prctl.h | 1 +
linux-user/sparc/target_prctl.h | 1 +
linux-user/x86_64/target_prctl.h | 1 +
linux-user/xtensa/target_prctl.h | 1 +
linux-user/syscall.c | 433 +++++++++------------------
24 files changed, 414 insertions(+), 320 deletions(-)
create mode 100644 linux-user/aarch64/target_prctl.h
create mode 100644 linux-user/alpha/target_prctl.h
create mode 100644 linux-user/arm/target_prctl.h
create mode 100644 linux-user/cris/target_prctl.h
create mode 100644 linux-user/hexagon/target_prctl.h
create mode 100644 linux-user/hppa/target_prctl.h
create mode 100644 linux-user/i386/target_prctl.h
create mode 100644 linux-user/m68k/target_prctl.h
create mode 100644 linux-user/microblaze/target_prctl.h
create mode 100644 linux-user/mips/target_prctl.h
create mode 100644 linux-user/mips64/target_prctl.h
create mode 100644 linux-user/nios2/target_prctl.h
create mode 100644 linux-user/openrisc/target_prctl.h
create mode 100644 linux-user/ppc/target_prctl.h
create mode 100644 linux-user/riscv/target_prctl.h
create mode 100644 linux-user/s390x/target_prctl.h
create mode 100644 linux-user/sh4/target_prctl.h
create mode 100644 linux-user/sparc/target_prctl.h
create mode 100644 linux-user/x86_64/target_prctl.h
create mode 100644 linux-user/xtensa/target_prctl.h
diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
new file mode 100644
index 0000000000..3f5a5d3933
--- /dev/null
+++ b/linux-user/aarch64/target_prctl.h
@@ -0,0 +1,160 @@
+/*
+ * AArch64 specific prctl functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef AARCH64_TARGET_PRCTL_H
+#define AARCH64_TARGET_PRCTL_H
+
+static abi_long do_prctl_get_vl(CPUArchState *env)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ if (cpu_isar_feature(aa64_sve, cpu)) {
+ return ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_get_vl do_prctl_get_vl
+
+static abi_long do_prctl_set_vl(CPUArchState *env, abi_long arg2)
+{
+ /*
+ * We cannot support either PR_SVE_SET_VL_ONEXEC or PR_SVE_VL_INHERIT.
+ * Note the kernel definition of sve_vl_valid allows for VQ=512,
+ * i.e. VL=8192, even though the current architectural maximum is VQ=16.
+ */
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))
+ && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
+ ARMCPU *cpu = env_archcpu(env);
+ uint32_t vq, old_vq;
+
+ old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
+ vq = MAX(arg2 / 16, 1);
+ vq = MIN(vq, cpu->sve_max_vq);
+
+ if (vq < old_vq) {
+ aarch64_sve_narrow_vq(env, vq);
+ }
+ env->vfp.zcr_el[1] = vq - 1;
+ arm_rebuild_hflags(env);
+ return vq * 16;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_set_vl do_prctl_set_vl
+
+static abi_long do_prctl_reset_keys(CPUArchState *env, abi_long arg2)
+{
+ ARMCPU *cpu = env_archcpu(env);
+
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ int all = (PR_PAC_APIAKEY | PR_PAC_APIBKEY |
+ PR_PAC_APDAKEY | PR_PAC_APDBKEY | PR_PAC_APGAKEY);
+ int ret = 0;
+ Error *err = NULL;
+
+ if (arg2 == 0) {
+ arg2 = all;
+ } else if (arg2 & ~all) {
+ return -TARGET_EINVAL;
+ }
+ if (arg2 & PR_PAC_APIAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apia,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APIBKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apib,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APDAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apda,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APDBKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apdb,
+ sizeof(ARMPACKey), &err);
+ }
+ if (arg2 & PR_PAC_APGAKEY) {
+ ret |= qemu_guest_getrandom(&env->keys.apga,
+ sizeof(ARMPACKey), &err);
+ }
+ if (ret != 0) {
+ /*
+ * Some unknown failure in the crypto. The best
+ * we can do is log it and fail the syscall.
+ * The real syscall cannot fail this way.
+ */
+ qemu_log_mask(LOG_UNIMP, "PR_PAC_RESET_KEYS: Crypto failure: %s",
+ error_get_pretty(err));
+ error_free(err);
+ return -TARGET_EIO;
+ }
+ return 0;
+ }
+ return -TARGET_EINVAL;
+}
+#define do_prctl_reset_keys do_prctl_reset_keys
+
+static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
+{
+ abi_ulong valid_mask = PR_TAGGED_ADDR_ENABLE;
+ ARMCPU *cpu = env_archcpu(env);
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ valid_mask |= PR_MTE_TCF_MASK;
+ valid_mask |= PR_MTE_TAG_MASK;
+ }
+
+ if (arg2 & ~valid_mask) {
+ return -TARGET_EINVAL;
+ }
+ env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
+
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ switch (arg2 & PR_MTE_TCF_MASK) {
+ case PR_MTE_TCF_NONE:
+ case PR_MTE_TCF_SYNC:
+ case PR_MTE_TCF_ASYNC:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
+ * Note that the syscall values are consistent with hw.
+ */
+ env->cp15.sctlr_el[1] =
+ deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
+
+ /*
+ * Write PR_MTE_TAG to GCR_EL1[Exclude].
+ * Note that the syscall uses an include mask,
+ * and hardware uses an exclude mask -- invert.
+ */
+ env->cp15.gcr_el1 =
+ deposit64(env->cp15.gcr_el1, 0, 16, ~arg2 >> PR_MTE_TAG_SHIFT);
+ arm_rebuild_hflags(env);
+ }
+ return 0;
+}
+#define do_prctl_set_tagged_addr_ctrl do_prctl_set_tagged_addr_ctrl
+
+static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchState *env)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ abi_long ret = 0;
+
+ if (env->tagged_addr_enable) {
+ ret |= PR_TAGGED_ADDR_ENABLE;
+ }
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ /* See do_prctl_set_tagged_addr_ctrl. */
+ ret |= extract64(env->cp15.sctlr_el[1], 38, 2) << PR_MTE_TCF_SHIFT;
+ ret = deposit64(ret, PR_MTE_TAG_SHIFT, 16, ~env->cp15.gcr_el1);
+ }
+ return ret;
+}
+#define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl
+
+#endif /* AARCH64_TARGET_PRCTL_H */
diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h
index 76f6c3391d..819f112ab0 100644
--- a/linux-user/aarch64/target_syscall.h
+++ b/linux-user/aarch64/target_syscall.h
@@ -20,27 +20,4 @@ struct target_pt_regs {
#define TARGET_MCL_FUTURE 2
#define TARGET_MCL_ONFAULT 4
-#define TARGET_PR_SVE_SET_VL 50
-#define TARGET_PR_SVE_GET_VL 51
-
-#define TARGET_PR_PAC_RESET_KEYS 54
-# define TARGET_PR_PAC_APIAKEY (1 << 0)
-# define TARGET_PR_PAC_APIBKEY (1 << 1)
-# define TARGET_PR_PAC_APDAKEY (1 << 2)
-# define TARGET_PR_PAC_APDBKEY (1 << 3)
-# define TARGET_PR_PAC_APGAKEY (1 << 4)
-
-#define TARGET_PR_SET_TAGGED_ADDR_CTRL 55
-#define TARGET_PR_GET_TAGGED_ADDR_CTRL 56
-# define TARGET_PR_TAGGED_ADDR_ENABLE (1UL << 0)
-/* MTE tag check fault modes */
-# define TARGET_PR_MTE_TCF_SHIFT 1
-# define TARGET_PR_MTE_TCF_NONE (0UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_SYNC (1UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_ASYNC (2UL << TARGET_PR_MTE_TCF_SHIFT)
-# define TARGET_PR_MTE_TCF_MASK (3UL << TARGET_PR_MTE_TCF_SHIFT)
-/* MTE tag inclusion mask */
-# define TARGET_PR_MTE_TAG_SHIFT 3
-# define TARGET_PR_MTE_TAG_MASK (0xffffUL << TARGET_PR_MTE_TAG_SHIFT)
-
#endif /* AARCH64_TARGET_SYSCALL_H */
diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/alpha/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/arm/target_prctl.h b/linux-user/arm/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/arm/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/cris/target_prctl.h b/linux-user/cris/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/cris/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/hexagon/target_prctl.h b/linux-user/hexagon/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/hexagon/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/hppa/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/i386/target_prctl.h b/linux-user/i386/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/i386/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/m68k/target_prctl.h b/linux-user/m68k/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/m68k/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/microblaze/target_prctl.h b/linux-user/microblaze/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/microblaze/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/mips/target_prctl.h b/linux-user/mips/target_prctl.h
new file mode 100644
index 0000000000..e028333db9
--- /dev/null
+++ b/linux-user/mips/target_prctl.h
@@ -0,0 +1,88 @@
+/*
+ * MIPS specific prctl functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef MIPS_TARGET_PRCTL_H
+#define MIPS_TARGET_PRCTL_H
+
+static abi_long do_prctl_get_fp_mode(CPUArchState *env)
+{
+ abi_long ret = 0;
+
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ ret |= PR_FP_MODE_FR;
+ }
+ if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
+ ret |= PR_FP_MODE_FRE;
+ }
+ return ret;
+}
+#define do_prctl_get_fp_mode do_prctl_get_fp_mode
+
+static abi_long do_prctl_set_fp_mode(CPUArchState *env, abi_long arg2)
+{
+ bool old_fr = env->CP0_Status & (1 << CP0St_FR);
+ bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
+ bool new_fr = arg2 & PR_FP_MODE_FR;
+ bool new_fre = arg2 & PR_FP_MODE_FRE;
+ const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
+
+ /* If nothing to change, return right away, successfully. */
+ if (old_fr == new_fr && old_fre == new_fre) {
+ return 0;
+ }
+ /* Check the value is valid */
+ if (arg2 & ~known_bits) {
+ return -TARGET_EOPNOTSUPP;
+ }
+ /* Setting FRE without FR is not supported. */
+ if (new_fre && !new_fr) {
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+ /* FR1 is not supported */
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
+ && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
+ /* cannot set FR=0 */
+ return -TARGET_EOPNOTSUPP;
+ }
+ if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
+ /* Cannot set FRE=1 */
+ return -TARGET_EOPNOTSUPP;
+ }
+
+ int i;
+ fpr_t *fpr = env->active_fpu.fpr;
+ for (i = 0; i < 32 ; i += 2) {
+ if (!old_fr && new_fr) {
+ fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
+ } else if (old_fr && !new_fr) {
+ fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
+ }
+ }
+
+ if (new_fr) {
+ env->CP0_Status |= (1 << CP0St_FR);
+ env->hflags |= MIPS_HFLAG_F64;
+ } else {
+ env->CP0_Status &= ~(1 << CP0St_FR);
+ env->hflags &= ~MIPS_HFLAG_F64;
+ }
+ if (new_fre) {
+ env->CP0_Config5 |= (1 << CP0C5_FRE);
+ if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+ env->hflags |= MIPS_HFLAG_FRE;
+ }
+ } else {
+ env->CP0_Config5 &= ~(1 << CP0C5_FRE);
+ env->hflags &= ~MIPS_HFLAG_FRE;
+ }
+
+ return 0;
+}
+#define do_prctl_set_fp_mode do_prctl_set_fp_mode
+
+#endif /* MIPS_TARGET_PRCTL_H */
diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
index f59057493a..1ce0a5bbf4 100644
--- a/linux-user/mips/target_syscall.h
+++ b/linux-user/mips/target_syscall.h
@@ -36,10 +36,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
return 0x40000;
}
-/* MIPS-specific prctl() options */
-#define TARGET_PR_SET_FP_MODE 45
-#define TARGET_PR_GET_FP_MODE 46
-#define TARGET_PR_FP_MODE_FR (1 << 0)
-#define TARGET_PR_FP_MODE_FRE (1 << 1)
-
#endif /* MIPS_TARGET_SYSCALL_H */
diff --git a/linux-user/mips64/target_prctl.h b/linux-user/mips64/target_prctl.h
new file mode 100644
index 0000000000..18da9ae619
--- /dev/null
+++ b/linux-user/mips64/target_prctl.h
@@ -0,0 +1 @@
+#include "../mips/target_prctl.h"
diff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h
index cd1e1b4969..74f12365bc 100644
--- a/linux-user/mips64/target_syscall.h
+++ b/linux-user/mips64/target_syscall.h
@@ -33,10 +33,4 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
return 0x40000;
}
-/* MIPS-specific prctl() options */
-#define TARGET_PR_SET_FP_MODE 45
-#define TARGET_PR_GET_FP_MODE 46
-#define TARGET_PR_FP_MODE_FR (1 << 0)
-#define TARGET_PR_FP_MODE_FRE (1 << 1)
-
#endif /* MIPS64_TARGET_SYSCALL_H */
diff --git a/linux-user/nios2/target_prctl.h b/linux-user/nios2/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/nios2/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/openrisc/target_prctl.h b/linux-user/openrisc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/openrisc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/ppc/target_prctl.h b/linux-user/ppc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/ppc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/riscv/target_prctl.h b/linux-user/riscv/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/riscv/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/s390x/target_prctl.h b/linux-user/s390x/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/s390x/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/sh4/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/sparc/target_prctl.h b/linux-user/sparc/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/sparc/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/x86_64/target_prctl.h b/linux-user/x86_64/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/x86_64/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/xtensa/target_prctl.h b/linux-user/xtensa/target_prctl.h
new file mode 100644
index 0000000000..eb53b31ad5
--- /dev/null
+++ b/linux-user/xtensa/target_prctl.h
@@ -0,0 +1 @@
+/* No special prctl support required. */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 544f5b662f..a417396981 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6291,9 +6291,155 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
return ret;
}
#endif /* defined(TARGET_ABI32 */
-
#endif /* defined(TARGET_I386) */
+/*
+ * These constants are generic. Supply any that are missing from the host.
+ */
+#ifndef PR_SET_NAME
+# define PR_SET_NAME 15
+# define PR_GET_NAME 16
+#endif
+#ifndef PR_SET_FP_MODE
+# define PR_SET_FP_MODE 45
+# define PR_GET_FP_MODE 46
+# define PR_FP_MODE_FR (1 << 0)
+# define PR_FP_MODE_FRE (1 << 1)
+#endif
+#ifndef PR_SVE_SET_VL
+# define PR_SVE_SET_VL 50
+# define PR_SVE_GET_VL 51
+# define PR_SVE_VL_LEN_MASK 0xffff
+# define PR_SVE_VL_INHERIT (1 << 17)
+#endif
+#ifndef PR_PAC_RESET_KEYS
+# define PR_PAC_RESET_KEYS 54
+# define PR_PAC_APIAKEY (1 << 0)
+# define PR_PAC_APIBKEY (1 << 1)
+# define PR_PAC_APDAKEY (1 << 2)
+# define PR_PAC_APDBKEY (1 << 3)
+# define PR_PAC_APGAKEY (1 << 4)
+#endif
+#ifndef PR_SET_TAGGED_ADDR_CTRL
+# define PR_SET_TAGGED_ADDR_CTRL 55
+# define PR_GET_TAGGED_ADDR_CTRL 56
+# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
+#endif
+#ifndef PR_MTE_TCF_SHIFT
+# define PR_MTE_TCF_SHIFT 1
+# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TAG_SHIFT 3
+# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
+#endif
+
+#include "target_prctl.h"
+
+static abi_long do_prctl_inval0(CPUArchState *env)
+{
+ return -TARGET_EINVAL;
+}
+
+static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
+{
+ return -TARGET_EINVAL;
+}
+
+#ifndef do_prctl_get_fp_mode
+#define do_prctl_get_fp_mode do_prctl_inval0
+#endif
+#ifndef do_prctl_set_fp_mode
+#define do_prctl_set_fp_mode do_prctl_inval1
+#endif
+#ifndef do_prctl_get_vl
+#define do_prctl_get_vl do_prctl_inval0
+#endif
+#ifndef do_prctl_set_vl
+#define do_prctl_set_vl do_prctl_inval1
+#endif
+#ifndef do_prctl_reset_keys
+#define do_prctl_reset_keys do_prctl_inval1
+#endif
+#ifndef do_prctl_set_tagged_addr_ctrl
+#define do_prctl_set_tagged_addr_ctrl do_prctl_inval1
+#endif
+#ifndef do_prctl_get_tagged_addr_ctrl
+#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
+#endif
+
+static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5)
+{
+ abi_long ret;
+
+ switch (option) {
+ case PR_GET_PDEATHSIG:
+ {
+ int deathsig;
+ ret = get_errno(prctl(PR_GET_PDEATHSIG, &deathsig,
+ arg3, arg4, arg5));
+ if (!is_error(ret) && arg2 && put_user_s32(deathsig, arg2)) {
+ return -TARGET_EFAULT;
+ }
+ return ret;
+ }
+ case PR_GET_NAME:
+ {
+ void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
+ if (!name) {
+ return -TARGET_EFAULT;
+ }
+ ret = get_errno(prctl(PR_GET_NAME, (uintptr_t)name,
+ arg3, arg4, arg5));
+ unlock_user(name, arg2, 16);
+ return ret;
+ }
+ case PR_SET_NAME:
+ {
+ void *name = lock_user(VERIFY_READ, arg2, 16, 1);
+ if (!name) {
+ return -TARGET_EFAULT;
+ }
+ ret = get_errno(prctl(PR_SET_NAME, (uintptr_t)name,
+ arg3, arg4, arg5));
+ unlock_user(name, arg2, 0);
+ return ret;
+ }
+ case PR_GET_FP_MODE:
+ return do_prctl_get_fp_mode(env);
+ case PR_SET_FP_MODE:
+ return do_prctl_set_fp_mode(env, arg2);
+ case PR_SVE_GET_VL:
+ return do_prctl_get_vl(env);
+ case PR_SVE_SET_VL:
+ return do_prctl_set_vl(env, arg2);
+ case PR_PAC_RESET_KEYS:
+ if (arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_reset_keys(env, arg2);
+ case PR_SET_TAGGED_ADDR_CTRL:
+ if (arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_set_tagged_addr_ctrl(env, arg2);
+ case PR_GET_TAGGED_ADDR_CTRL:
+ if (arg2 || arg3 || arg4 || arg5) {
+ return -TARGET_EINVAL;
+ }
+ return do_prctl_get_tagged_addr_ctrl(env);
+ case PR_GET_SECCOMP:
+ case PR_SET_SECCOMP:
+ /* Disable seccomp to prevent the target disabling syscalls we need. */
+ return -TARGET_EINVAL;
+ default:
+ /* Most prctl options have no pointer arguments */
+ return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+ }
+}
+
#define NEW_STACK_SIZE 0x40000
@@ -10630,290 +10776,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
return ret;
#endif
case TARGET_NR_prctl:
- switch (arg1) {
- case PR_GET_PDEATHSIG:
- {
- int deathsig;
- ret = get_errno(prctl(arg1, &deathsig, arg3, arg4, arg5));
- if (!is_error(ret) && arg2
- && put_user_s32(deathsig, arg2)) {
- return -TARGET_EFAULT;
- }
- return ret;
- }
-#ifdef PR_GET_NAME
- case PR_GET_NAME:
- {
- void *name = lock_user(VERIFY_WRITE, arg2, 16, 1);
- if (!name) {
- return -TARGET_EFAULT;
- }
- ret = get_errno(prctl(arg1, (unsigned long)name,
- arg3, arg4, arg5));
- unlock_user(name, arg2, 16);
- return ret;
- }
- case PR_SET_NAME:
- {
- void *name = lock_user(VERIFY_READ, arg2, 16, 1);
- if (!name) {
- return -TARGET_EFAULT;
- }
- ret = get_errno(prctl(arg1, (unsigned long)name,
- arg3, arg4, arg5));
- unlock_user(name, arg2, 0);
- return ret;
- }
-#endif
-#ifdef TARGET_MIPS
- case TARGET_PR_GET_FP_MODE:
- {
- CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
- ret = 0;
- if (env->CP0_Status & (1 << CP0St_FR)) {
- ret |= TARGET_PR_FP_MODE_FR;
- }
- if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
- ret |= TARGET_PR_FP_MODE_FRE;
- }
- return ret;
- }
- case TARGET_PR_SET_FP_MODE:
- {
- CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
- bool old_fr = env->CP0_Status & (1 << CP0St_FR);
- bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
- bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
- bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
-
- const unsigned int known_bits = TARGET_PR_FP_MODE_FR |
- TARGET_PR_FP_MODE_FRE;
-
- /* If nothing to change, return right away, successfully. */
- if (old_fr == new_fr && old_fre == new_fre) {
- return 0;
- }
- /* Check the value is valid */
- if (arg2 & ~known_bits) {
- return -TARGET_EOPNOTSUPP;
- }
- /* Setting FRE without FR is not supported. */
- if (new_fre && !new_fr) {
- return -TARGET_EOPNOTSUPP;
- }
- if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
- /* FR1 is not supported */
- return -TARGET_EOPNOTSUPP;
- }
- if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
- && !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
- /* cannot set FR=0 */
- return -TARGET_EOPNOTSUPP;
- }
- if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
- /* Cannot set FRE=1 */
- return -TARGET_EOPNOTSUPP;
- }
-
- int i;
- fpr_t *fpr = env->active_fpu.fpr;
- for (i = 0; i < 32 ; i += 2) {
- if (!old_fr && new_fr) {
- fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
- } else if (old_fr && !new_fr) {
- fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
- }
- }
-
- if (new_fr) {
- env->CP0_Status |= (1 << CP0St_FR);
- env->hflags |= MIPS_HFLAG_F64;
- } else {
- env->CP0_Status &= ~(1 << CP0St_FR);
- env->hflags &= ~MIPS_HFLAG_F64;
- }
- if (new_fre) {
- env->CP0_Config5 |= (1 << CP0C5_FRE);
- if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
- env->hflags |= MIPS_HFLAG_FRE;
- }
- } else {
- env->CP0_Config5 &= ~(1 << CP0C5_FRE);
- env->hflags &= ~MIPS_HFLAG_FRE;
- }
-
- return 0;
- }
-#endif /* MIPS */
-#ifdef TARGET_AARCH64
- case TARGET_PR_SVE_SET_VL:
- /*
- * We cannot support either PR_SVE_SET_VL_ONEXEC or
- * PR_SVE_VL_INHERIT. Note the kernel definition
- * of sve_vl_valid allows for VQ=512, i.e. VL=8192,
- * even though the current architectural maximum is VQ=16.
- */
- ret = -TARGET_EINVAL;
- if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env))
- && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
- uint32_t vq, old_vq;
-
- old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
- vq = MAX(arg2 / 16, 1);
- vq = MIN(vq, cpu->sve_max_vq);
-
- if (vq < old_vq) {
- aarch64_sve_narrow_vq(env, vq);
- }
- env->vfp.zcr_el[1] = vq - 1;
- arm_rebuild_hflags(env);
- ret = vq * 16;
- }
- return ret;
- case TARGET_PR_SVE_GET_VL:
- ret = -TARGET_EINVAL;
- {
- ARMCPU *cpu = env_archcpu(cpu_env);
- if (cpu_isar_feature(aa64_sve, cpu)) {
- ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16;
- }
- }
- return ret;
- case TARGET_PR_PAC_RESET_KEYS:
- {
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- if (cpu_isar_feature(aa64_pauth, cpu)) {
- int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY |
- TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY |
- TARGET_PR_PAC_APGAKEY);
- int ret = 0;
- Error *err = NULL;
-
- if (arg2 == 0) {
- arg2 = all;
- } else if (arg2 & ~all) {
- return -TARGET_EINVAL;
- }
- if (arg2 & TARGET_PR_PAC_APIAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apia,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APIBKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apib,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APDAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apda,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APDBKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apdb,
- sizeof(ARMPACKey), &err);
- }
- if (arg2 & TARGET_PR_PAC_APGAKEY) {
- ret |= qemu_guest_getrandom(&env->keys.apga,
- sizeof(ARMPACKey), &err);
- }
- if (ret != 0) {
- /*
- * Some unknown failure in the crypto. The best
- * we can do is log it and fail the syscall.
- * The real syscall cannot fail this way.
- */
- qemu_log_mask(LOG_UNIMP,
- "PR_PAC_RESET_KEYS: Crypto failure: %s",
- error_get_pretty(err));
- error_free(err);
- return -TARGET_EIO;
- }
- return 0;
- }
- }
- return -TARGET_EINVAL;
- case TARGET_PR_SET_TAGGED_ADDR_CTRL:
- {
- abi_ulong valid_mask = TARGET_PR_TAGGED_ADDR_ENABLE;
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (cpu_isar_feature(aa64_mte, cpu)) {
- valid_mask |= TARGET_PR_MTE_TCF_MASK;
- valid_mask |= TARGET_PR_MTE_TAG_MASK;
- }
-
- if ((arg2 & ~valid_mask) || arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- env->tagged_addr_enable = arg2 & TARGET_PR_TAGGED_ADDR_ENABLE;
-
- if (cpu_isar_feature(aa64_mte, cpu)) {
- switch (arg2 & TARGET_PR_MTE_TCF_MASK) {
- case TARGET_PR_MTE_TCF_NONE:
- case TARGET_PR_MTE_TCF_SYNC:
- case TARGET_PR_MTE_TCF_ASYNC:
- break;
- default:
- return -EINVAL;
- }
-
- /*
- * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
- * Note that the syscall values are consistent with hw.
- */
- env->cp15.sctlr_el[1] =
- deposit64(env->cp15.sctlr_el[1], 38, 2,
- arg2 >> TARGET_PR_MTE_TCF_SHIFT);
-
- /*
- * Write PR_MTE_TAG to GCR_EL1[Exclude].
- * Note that the syscall uses an include mask,
- * and hardware uses an exclude mask -- invert.
- */
- env->cp15.gcr_el1 =
- deposit64(env->cp15.gcr_el1, 0, 16,
- ~arg2 >> TARGET_PR_MTE_TAG_SHIFT);
- arm_rebuild_hflags(env);
- }
- return 0;
- }
- case TARGET_PR_GET_TAGGED_ADDR_CTRL:
- {
- abi_long ret = 0;
- CPUARMState *env = cpu_env;
- ARMCPU *cpu = env_archcpu(env);
-
- if (arg2 || arg3 || arg4 || arg5) {
- return -TARGET_EINVAL;
- }
- if (env->tagged_addr_enable) {
- ret |= TARGET_PR_TAGGED_ADDR_ENABLE;
- }
- if (cpu_isar_feature(aa64_mte, cpu)) {
- /* See above. */
- ret |= (extract64(env->cp15.sctlr_el[1], 38, 2)
- << TARGET_PR_MTE_TCF_SHIFT);
- ret = deposit64(ret, TARGET_PR_MTE_TAG_SHIFT, 16,
- ~env->cp15.gcr_el1);
- }
- return ret;
- }
-#endif /* AARCH64 */
- case PR_GET_SECCOMP:
- case PR_SET_SECCOMP:
- /* Disable seccomp to prevent the target disabling syscalls we
- * need. */
- return -TARGET_EINVAL;
- default:
- /* Most prctl options have no pointer arguments */
- return get_errno(prctl(arg1, arg2, arg3, arg4, arg5));
- }
+ return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5);
break;
#ifdef TARGET_NR_arch_prctl
case TARGET_NR_arch_prctl:
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 63/67] linux-user: Disable more prctl subcodes
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (61 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 62/67] linux-user: Split out do_prctl and subroutines Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
` (3 subsequent siblings)
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Create a list of subcodes that we want to pass on, a list of
subcodes that should not be passed on because they would affect
the running qemu itself, and a list that probably could be
implemented but require extra work. Do not pass on unknown subcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/syscall.c | 56 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 52 insertions(+), 4 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index a417396981..7635c2397a 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6334,6 +6334,13 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
# define PR_MTE_TAG_SHIFT 3
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
#endif
+#ifndef PR_SET_IO_FLUSHER
+# define PR_SET_IO_FLUSHER 57
+# define PR_GET_IO_FLUSHER 58
+#endif
+#ifndef PR_SET_SYSCALL_USER_DISPATCH
+# define PR_SET_SYSCALL_USER_DISPATCH 59
+#endif
#include "target_prctl.h"
@@ -6430,13 +6437,54 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
return -TARGET_EINVAL;
}
return do_prctl_get_tagged_addr_ctrl(env);
+
+ case PR_GET_DUMPABLE:
+ case PR_SET_DUMPABLE:
+ case PR_GET_KEEPCAPS:
+ case PR_SET_KEEPCAPS:
+ case PR_GET_TIMING:
+ case PR_SET_TIMING:
+ case PR_GET_TIMERSLACK:
+ case PR_SET_TIMERSLACK:
+ case PR_MCE_KILL:
+ case PR_MCE_KILL_GET:
+ case PR_GET_NO_NEW_PRIVS:
+ case PR_SET_NO_NEW_PRIVS:
+ case PR_GET_IO_FLUSHER:
+ case PR_SET_IO_FLUSHER:
+ /* Some prctl options have no pointer arguments and we can pass on. */
+ return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+
+ case PR_GET_CHILD_SUBREAPER:
+ case PR_SET_CHILD_SUBREAPER:
+ case PR_GET_SPECULATION_CTRL:
+ case PR_SET_SPECULATION_CTRL:
+ case PR_GET_TID_ADDRESS:
+ /* TODO */
+ return -TARGET_EINVAL;
+
+ case PR_GET_FPEXC:
+ case PR_SET_FPEXC:
+ /* Was used for SPE on PowerPC. */
+ return -TARGET_EINVAL;
+
+ case PR_GET_ENDIAN:
+ case PR_SET_ENDIAN:
+ case PR_GET_FPEMU:
+ case PR_SET_FPEMU:
+ case PR_SET_MM:
case PR_GET_SECCOMP:
case PR_SET_SECCOMP:
- /* Disable seccomp to prevent the target disabling syscalls we need. */
- return -TARGET_EINVAL;
+ case PR_SET_SYSCALL_USER_DISPATCH:
+ case PR_GET_THP_DISABLE:
+ case PR_SET_THP_DISABLE:
+ case PR_GET_TSC:
+ case PR_SET_TSC:
+ case PR_GET_UNALIGN:
+ case PR_SET_UNALIGN:
default:
- /* Most prctl options have no pointer arguments */
- return get_errno(prctl(option, arg2, arg3, arg4, arg5));
+ /* Disable to prevent the target disabling stuff we need. */
+ return -TARGET_EINVAL;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (62 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 63/67] linux-user: Disable more prctl subcodes Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 19:11 ` Warner Losh
2021-10-15 4:10 ` [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
` (2 subsequent siblings)
66 siblings, 1 reply; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
This requires extra work for each target, but adds the
common syscall code, and the necessary flag in CPUState.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 3 +++
linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++
cpu.c | 20 ++++++++++++-----
linux-user/syscall.c | 13 +++++++++--
4 files changed, 56 insertions(+), 7 deletions(-)
create mode 100644 linux-user/generic/target_prctl_unalign.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 1a10497af3..6202bbf9c3 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -412,6 +412,9 @@ struct CPUState {
bool ignore_memory_transaction_failures;
+ /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
+ bool prctl_unalign_sigbus;
+
struct hax_vcpu_state *hax_vcpu;
struct hvf_vcpu_state *hvf;
diff --git a/linux-user/generic/target_prctl_unalign.h b/linux-user/generic/target_prctl_unalign.h
new file mode 100644
index 0000000000..bc3b83af2a
--- /dev/null
+++ b/linux-user/generic/target_prctl_unalign.h
@@ -0,0 +1,27 @@
+/*
+ * Generic prctl unalign functions for linux-user
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H
+#define GENERIC_TARGET_PRCTL_UNALIGN_H
+
+static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2)
+{
+ CPUState *cs = env_cpu(env);
+ uint32_t res = PR_UNALIGN_NOPRINT;
+ if (cs->prctl_unalign_sigbus) {
+ res |= PR_UNALIGN_SIGBUS;
+ }
+ return put_user_u32(res, arg2);
+}
+#define do_prctl_get_unalign do_prctl_get_unalign
+
+static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2)
+{
+ env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS;
+ return 0;
+}
+#define do_prctl_set_unalign do_prctl_set_unalign
+
+#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */
diff --git a/cpu.c b/cpu.c
index 9bce67ef55..9e388d9cd3 100644
--- a/cpu.c
+++ b/cpu.c
@@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu)
cpu_list_remove(cpu);
}
+/*
+ * This can't go in hw/core/cpu.c because that file is compiled only
+ * once for both user-mode and system builds.
+ */
static Property cpu_common_props[] = {
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
/*
- * Create a memory property for softmmu CPU object,
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
- * because that file is compiled only once for both user-mode
- * and system builds.) The default if no link is set up is to use
+ * Create a property for the user-only object, so users can
+ * adjust prctl(PR_SET_UNALIGN) from the command-line.
+ * Has no effect if the target does not support the feature.
+ */
+ DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
+ prctl_unalign_sigbus, false),
+#else
+ /*
+ * Create a memory property for softmmu CPU object, so users can
+ * wire up its memory. The default if no link is set up is to use
* the system address space.
*/
DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 7635c2397a..ac3bc8a330 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env, abi_long arg2)
#ifndef do_prctl_get_tagged_addr_ctrl
#define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
#endif
+#ifndef do_prctl_get_unalign
+#define do_prctl_get_unalign do_prctl_inval1
+#endif
+#ifndef do_prctl_set_unalign
+#define do_prctl_set_unalign do_prctl_inval1
+#endif
static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
abi_long arg3, abi_long arg4, abi_long arg5)
@@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
}
return do_prctl_get_tagged_addr_ctrl(env);
+ case PR_GET_UNALIGN:
+ return do_prctl_get_unalign(env, arg2);
+ case PR_SET_UNALIGN:
+ return do_prctl_set_unalign(env, arg2);
+
case PR_GET_DUMPABLE:
case PR_SET_DUMPABLE:
case PR_GET_KEEPCAPS:
@@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,
case PR_SET_THP_DISABLE:
case PR_GET_TSC:
case PR_SET_TSC:
- case PR_GET_UNALIGN:
- case PR_SET_UNALIGN:
default:
/* Disable to prevent the target disabling stuff we need. */
return -TARGET_EINVAL;
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* Re: [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN
2021-10-15 4:10 ` [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
@ 2021-10-15 19:11 ` Warner Losh
0 siblings, 0 replies; 101+ messages in thread
From: Warner Losh @ 2021-10-15 19:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alex Bennée, QEMU Developers, Laurent Vivier
[-- Attachment #1: Type: text/plain, Size: 5020 bytes --]
On Thu, Oct 14, 2021 at 10:14 PM Richard Henderson <
richard.henderson@linaro.org> wrote:
> This requires extra work for each target, but adds the
> common syscall code, and the necessary flag in CPUState.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/cpu.h | 3 +++
> linux-user/generic/target_prctl_unalign.h | 27 +++++++++++++++++++++++
> cpu.c | 20 ++++++++++++-----
> linux-user/syscall.c | 13 +++++++++--
> 4 files changed, 56 insertions(+), 7 deletions(-)
> create mode 100644 linux-user/generic/target_prctl_unalign.h
>
Reviewed-by: Warner Losh <imp@bsdimp.com>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 1a10497af3..6202bbf9c3 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -412,6 +412,9 @@ struct CPUState {
>
> bool ignore_memory_transaction_failures;
>
> + /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */
> + bool prctl_unalign_sigbus;
> +
> struct hax_vcpu_state *hax_vcpu;
>
> struct hvf_vcpu_state *hvf;
> diff --git a/linux-user/generic/target_prctl_unalign.h
> b/linux-user/generic/target_prctl_unalign.h
> new file mode 100644
> index 0000000000..bc3b83af2a
> --- /dev/null
> +++ b/linux-user/generic/target_prctl_unalign.h
> @@ -0,0 +1,27 @@
> +/*
> + * Generic prctl unalign functions for linux-user
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +#ifndef GENERIC_TARGET_PRCTL_UNALIGN_H
> +#define GENERIC_TARGET_PRCTL_UNALIGN_H
> +
> +static abi_long do_prctl_get_unalign(CPUArchState *env, target_long arg2)
> +{
> + CPUState *cs = env_cpu(env);
> + uint32_t res = PR_UNALIGN_NOPRINT;
> + if (cs->prctl_unalign_sigbus) {
> + res |= PR_UNALIGN_SIGBUS;
> + }
> + return put_user_u32(res, arg2);
> +}
> +#define do_prctl_get_unalign do_prctl_get_unalign
> +
> +static abi_long do_prctl_set_unalign(CPUArchState *env, target_long arg2)
> +{
> + env_cpu(env)->prctl_unalign_sigbus = arg2 & PR_UNALIGN_SIGBUS;
> + return 0;
> +}
> +#define do_prctl_set_unalign do_prctl_set_unalign
> +
> +#endif /* GENERIC_TARGET_PRCTL_UNALIGN_H */
> diff --git a/cpu.c b/cpu.c
> index 9bce67ef55..9e388d9cd3 100644
> --- a/cpu.c
> +++ b/cpu.c
> @@ -179,13 +179,23 @@ void cpu_exec_unrealizefn(CPUState *cpu)
> cpu_list_remove(cpu);
> }
>
> +/*
> + * This can't go in hw/core/cpu.c because that file is compiled only
> + * once for both user-mode and system builds.
> + */
> static Property cpu_common_props[] = {
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> /*
> - * Create a memory property for softmmu CPU object,
> - * so users can wire up its memory. (This can't go in hw/core/cpu.c
> - * because that file is compiled only once for both user-mode
> - * and system builds.) The default if no link is set up is to use
> + * Create a property for the user-only object, so users can
> + * adjust prctl(PR_SET_UNALIGN) from the command-line.
> + * Has no effect if the target does not support the feature.
> + */
> + DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
> + prctl_unalign_sigbus, false),
> +#else
> + /*
> + * Create a memory property for softmmu CPU object, so users can
> + * wire up its memory. The default if no link is set up is to use
> * the system address space.
> */
> DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
> diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> index 7635c2397a..ac3bc8a330 100644
> --- a/linux-user/syscall.c
> +++ b/linux-user/syscall.c
> @@ -6375,6 +6375,12 @@ static abi_long do_prctl_inval1(CPUArchState *env,
> abi_long arg2)
> #ifndef do_prctl_get_tagged_addr_ctrl
> #define do_prctl_get_tagged_addr_ctrl do_prctl_inval0
> #endif
> +#ifndef do_prctl_get_unalign
> +#define do_prctl_get_unalign do_prctl_inval1
> +#endif
> +#ifndef do_prctl_set_unalign
> +#define do_prctl_set_unalign do_prctl_inval1
> +#endif
>
> static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long
> arg2,
> abi_long arg3, abi_long arg4, abi_long arg5)
> @@ -6438,6 +6444,11 @@ static abi_long do_prctl(CPUArchState *env,
> abi_long option, abi_long arg2,
> }
> return do_prctl_get_tagged_addr_ctrl(env);
>
> + case PR_GET_UNALIGN:
> + return do_prctl_get_unalign(env, arg2);
> + case PR_SET_UNALIGN:
> + return do_prctl_set_unalign(env, arg2);
> +
> case PR_GET_DUMPABLE:
> case PR_SET_DUMPABLE:
> case PR_GET_KEEPCAPS:
> @@ -6480,8 +6491,6 @@ static abi_long do_prctl(CPUArchState *env, abi_long
> option, abi_long arg2,
> case PR_SET_THP_DISABLE:
> case PR_GET_TSC:
> case PR_SET_TSC:
> - case PR_GET_UNALIGN:
> - case PR_SET_UNALIGN:
> default:
> /* Disable to prevent the target disabling stuff we need. */
> return -TARGET_EINVAL;
> --
> 2.25.1
>
>
[-- Attachment #2: Type: text/html, Size: 6276 bytes --]
^ permalink raw reply [flat|nested] 101+ messages in thread
* [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (63 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 64/67] linux-user: Add code for PR_GET/SET_UNALIGN Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 66/67] target/hppa: " Richard Henderson
2021-10-15 4:10 ` [PATCH v5 67/67] target/sh4: " Richard Henderson
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/alpha/target_prctl.h | 2 +-
target/alpha/cpu.h | 5 +++++
target/alpha/translate.c | 31 ++++++++++++++++++++++---------
3 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/linux-user/alpha/target_prctl.h b/linux-user/alpha/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/alpha/target_prctl.h
+++ b/linux-user/alpha/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index afd975c878..e819211503 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -383,6 +383,8 @@ enum {
#define ENV_FLAG_TB_MASK \
(ENV_FLAG_PAL_MODE | ENV_FLAG_PS_USER | ENV_FLAG_FEN)
+#define TB_FLAG_UNALIGN (1u << 1)
+
static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
{
int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
@@ -470,6 +472,9 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
*pflags = env->flags & ENV_FLAG_TB_MASK;
+#ifdef CONFIG_USER_ONLY
+ *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
}
#ifdef CONFIG_USER_ONLY
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 0eee3a1bcc..2656037b8b 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -45,7 +45,9 @@ typedef struct DisasContext DisasContext;
struct DisasContext {
DisasContextBase base;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ MemOp unalign;
+#else
uint64_t palbr;
#endif
uint32_t tbflags;
@@ -68,6 +70,12 @@ struct DisasContext {
TCGv sink;
};
+#ifdef CONFIG_USER_ONLY
+#define UNALIGN(C) (C)->unalign
+#else
+#define UNALIGN(C) 0
+#endif
+
/* Target-specific return values from translate_one, indicating the
state of the TB. Note that DISAS_NEXT indicates that we are not
exiting the TB. */
@@ -270,7 +278,7 @@ static inline DisasJumpType gen_invalid(DisasContext *ctx)
static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
gen_helper_memory_to_f(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
@@ -278,7 +286,7 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv addr)
static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv tmp = tcg_temp_new();
- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
gen_helper_memory_to_g(dest, tmp);
tcg_temp_free(tmp);
}
@@ -286,14 +294,14 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr)
static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
gen_helper_memory_to_s(dest, tmp32);
tcg_temp_free_i32(tmp32);
}
static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr)
{
- tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
}
static void gen_load_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
@@ -324,6 +332,8 @@ static void gen_load_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
tcg_gen_andi_i64(addr, addr, ~0x7);
+ } else if (!locked) {
+ op |= UNALIGN(ctx);
}
dest = ctx->ir[ra];
@@ -340,7 +350,7 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
gen_helper_f_to_memory(tmp32, addr);
- tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
tcg_temp_free_i32(tmp32);
}
@@ -348,7 +358,7 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv tmp = tcg_temp_new();
gen_helper_g_to_memory(tmp, src);
- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
tcg_temp_free(tmp);
}
@@ -356,13 +366,13 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
gen_helper_s_to_memory(tmp32, src);
- tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL);
+ tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx));
tcg_temp_free_i32(tmp32);
}
static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr)
{
- tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ);
+ tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, MO_LEQ | UNALIGN(ctx));
}
static void gen_store_fp(DisasContext *ctx, int ra, int rb, int32_t disp16,
@@ -383,6 +393,8 @@ static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp16,
tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16);
if (clear) {
tcg_gen_andi_i64(addr, addr, ~0x7);
+ } else {
+ op |= UNALIGN(ctx);
}
src = load_gpr(ctx, ra);
@@ -2942,6 +2954,7 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
#ifdef CONFIG_USER_ONLY
ctx->ir = cpu_std_ir;
+ ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->palbr = env->palbr;
ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 66/67] target/hppa: Implement prctl_unalign_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (64 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 65/67] target/alpha: Implement prctl_unalign_sigbus Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
2021-10-15 4:10 ` [PATCH v5 67/67] target/sh4: " Richard Henderson
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/target_prctl.h | 2 +-
target/hppa/cpu.h | 5 ++++-
target/hppa/translate.c | 19 +++++++++++++++----
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/linux-user/hppa/target_prctl.h b/linux-user/hppa/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/hppa/target_prctl.h
+++ b/linux-user/hppa/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 294fd7297f..45fd338b02 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -259,12 +259,14 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
return hppa_form_gva_psw(env->psw, spc, off);
}
-/* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
+/*
+ * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
* same value.
*/
#define TB_FLAG_SR_SAME PSW_I
#define TB_FLAG_PRIV_SHIFT 8
+#define TB_FLAG_UNALIGN 0x400
static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
target_ulong *cs_base,
@@ -279,6 +281,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
#ifdef CONFIG_USER_ONLY
*pc = env->iaoq_f & -4;
*cs_base = env->iaoq_b & -4;
+ flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
#else
/* ??? E, T, H, L, B, P bits need to be here, when implemented. */
flags |= env->psw & (PSW_W | PSW_C | PSW_D);
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index c3698cf067..fdaa2b12b8 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -272,8 +272,18 @@ typedef struct DisasContext {
int mmu_idx;
int privilege;
bool psw_n_nonzero;
+
+#ifdef CONFIG_USER_ONLY
+ MemOp unalign;
+#endif
} DisasContext;
+#ifdef CONFIG_USER_ONLY
+#define UNALIGN(C) (C)->unalign
+#else
+#define UNALIGN(C) 0
+#endif
+
/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
static int expand_sm_imm(DisasContext *ctx, int val)
{
@@ -1477,7 +1487,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1495,7 +1505,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_ld_i64(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1513,7 +1523,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_st_i32(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -1531,7 +1541,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb,
form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify,
ctx->mmu_idx == MMU_PHYS_IDX);
- tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop);
+ tcg_gen_qemu_st_i64(src, addr, ctx->mmu_idx, mop | UNALIGN(ctx));
if (modify) {
save_gpr(ctx, rb, ofs);
}
@@ -4110,6 +4120,7 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mmu_idx = MMU_USER_IDX;
ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX;
ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX;
+ ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3;
ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX);
--
2.25.1
^ permalink raw reply related [flat|nested] 101+ messages in thread* [PATCH v5 67/67] target/sh4: Implement prctl_unalign_sigbus
2021-10-15 4:09 [PATCH v5 00/67] user-only: Cleanup SIGSEGV and SIGBUS handling Richard Henderson
` (65 preceding siblings ...)
2021-10-15 4:10 ` [PATCH v5 66/67] target/hppa: " Richard Henderson
@ 2021-10-15 4:10 ` Richard Henderson
66 siblings, 0 replies; 101+ messages in thread
From: Richard Henderson @ 2021-10-15 4:10 UTC (permalink / raw)
To: qemu-devel; +Cc: alex.bennee, laurent, imp
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.
The Linux kernel does not handle all memory operations: no
floating-point and no MAC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sh4/target_prctl.h | 2 +-
target/sh4/cpu.h | 4 +++
target/sh4/translate.c | 50 ++++++++++++++++++++++++-----------
3 files changed, 39 insertions(+), 17 deletions(-)
diff --git a/linux-user/sh4/target_prctl.h b/linux-user/sh4/target_prctl.h
index eb53b31ad5..5629ddbf39 100644
--- a/linux-user/sh4/target_prctl.h
+++ b/linux-user/sh4/target_prctl.h
@@ -1 +1 @@
-/* No special prctl support required. */
+#include "../generic/target_prctl_unalign.h"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 4cfb109f56..fb9dd9db2f 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -83,6 +83,7 @@
#define DELAY_SLOT_RTE (1 << 2)
#define TB_FLAG_PENDING_MOVCA (1 << 3)
+#define TB_FLAG_UNALIGN (1 << 4)
#define GUSA_SHIFT 4
#ifdef CONFIG_USER_ONLY
@@ -373,6 +374,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
| (env->sr & (1u << SR_FD)) /* Bit 15 */
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+ *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
}
#endif /* SH4_CPU_H */
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index d363050272..7965db586f 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -50,8 +50,10 @@ typedef struct DisasContext {
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
+#define UNALIGN(C) (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0)
#else
#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
+#define UNALIGN(C) 0
#endif
/* Target-specific values for ctx->base.is_jmp. */
@@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
return;
case 0x2001: /* mov.w Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
return;
case 0x2002: /* mov.l Rm,@Rn */
- tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
return;
case 0x6000: /* mov.b @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
return;
case 0x6001: /* mov.w @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
return;
case 0x6002: /* mov.l @Rm,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
return;
case 0x2004: /* mov.b Rm,@-Rn */
{
@@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
return;
case 0x6005: /* mov.w @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
case 0x6006: /* mov.l @Rm+,Rn */
- tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
return;
@@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
- tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+ MO_TEUL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
- tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+ tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+ MO_TESL | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
+ tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
+ MO_TEUW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
@@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
- tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
+ tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
+ MO_TESW | UNALIGN(ctx));
tcg_temp_free(addr);
}
return;
--
2.25.1
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