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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 17/24] target/riscv: Remove dead code after exception
Date: Sat, 16 Oct 2021 11:15:07 -0700	[thread overview]
Message-ID: <20211016181514.3165661-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211016181514.3165661-1-richard.henderson@linaro.org>

We have already set DISAS_NORETURN in generate_exception,
which makes the exit_tb unreachable.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 32312be202..a7afcb15ce 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -22,8 +22,6 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
 {
     /* always generates U-level ECALL, fixed in do_interrupt handler */
     generate_exception(ctx, RISCV_EXCP_U_ECALL);
-    exit_tb(ctx); /* no chaining */
-    ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
 
@@ -60,13 +58,11 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
         post   = opcode_at(&ctx->base, post_addr);
     }
 
-    if  (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+    if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
-    exit_tb(ctx); /* no chaining */
-    ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 }
 
-- 
2.25.1



  parent reply	other threads:[~2021-10-16 18:36 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-16 18:14 [PULL 00/24] tcg patch queue Richard Henderson
2021-10-16 18:14 ` [PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec Richard Henderson
2021-10-16 18:14 ` [PULL 02/24] target/alpha: Drop checks for singlestep_enabled Richard Henderson
2021-10-16 18:14 ` [PULL 03/24] target/avr: " Richard Henderson
2021-10-16 18:14 ` [PULL 04/24] target/cris: " Richard Henderson
2021-10-16 18:14 ` [PULL 05/24] target/hexagon: " Richard Henderson
2021-10-16 18:14 ` [PULL 06/24] target/arm: " Richard Henderson
2021-10-16 18:14 ` [PULL 07/24] target/hppa: " Richard Henderson
2021-10-16 18:14 ` [PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt Richard Henderson
2021-10-16 18:14 ` [PULL 09/24] target/i386: Drop check for singlestep_enabled Richard Henderson
2021-10-16 18:15 ` [PULL 10/24] target/m68k: Drop checks " Richard Henderson
2021-10-16 18:15 ` [PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP Richard Henderson
2021-10-16 18:15 ` [PULL 12/24] target/microblaze: Drop checks for singlestep_enabled Richard Henderson
2021-10-16 18:15 ` [PULL 13/24] target/mips: Fix single stepping Richard Henderson
2021-10-16 18:15 ` [PULL 14/24] target/mips: Drop exit checks for singlestep_enabled Richard Henderson
2021-10-16 18:15 ` [PULL 15/24] target/openrisc: Drop " Richard Henderson
2021-10-16 18:15 ` [PULL 16/24] target/ppc: Drop exit " Richard Henderson
2021-10-16 18:15 ` Richard Henderson [this message]
2021-10-16 18:15 ` [PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr Richard Henderson
2021-10-16 18:15 ` [PULL 19/24] target/rx: Drop checks for singlestep_enabled Richard Henderson
2021-10-16 18:15 ` [PULL 20/24] target/s390x: Drop check " Richard Henderson
2021-10-16 18:15 ` [PULL 21/24] target/sh4: " Richard Henderson
2021-10-16 18:15 ` [PULL 22/24] target/tricore: " Richard Henderson
2021-10-16 18:15 ` [PULL 23/24] target/xtensa: " Richard Henderson
2021-10-16 18:15 ` [PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c" Richard Henderson
2021-10-16 23:49 ` [PULL 00/24] tcg patch queue Richard Henderson

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