From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org,
sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
space.monkey.delivers@gmail.com,
Alistair Francis <alistair.francis@wdc.com>,
kupokupokupopo@gmail.com, palmer@dabbelt.com,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v14 8/8] [RISCV_PM] Allow experimental J-ext to be turned on
Date: Sun, 17 Oct 2021 20:27:28 +0300 [thread overview]
Message-ID: <20211017172728.759687-9-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20211017172728.759687-1-space.monkey.delivers@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7f9dde70b7..fb08c0ffb8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -558,6 +558,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_vext_version(env, vext_version);
}
+ if (cpu->cfg.ext_j) {
+ target_misa |= RVJ;
+ }
set_misa(env, target_misa);
}
@@ -624,6 +627,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
--
2.30.2
prev parent reply other threads:[~2021-10-17 17:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-17 17:27 [PATCH v14 0/8] RISC-V Pointer Masking implementation Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 1/8] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 2/8] [RISCV_PM] Add CSR defines for RISC-V PM extension Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 3/8] [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode Alexey Baturo
2021-10-19 22:27 ` Alistair Francis
2021-10-17 17:27 ` [PATCH v14 4/8] [RISCV_PM] Add J extension state description Alexey Baturo
2021-10-19 6:53 ` Alistair Francis
2021-10-19 7:02 ` Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 5/8] [RISCV_PM] Print new PM CSRs in QEMU logs Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 6/8] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2021-10-17 17:27 ` [PATCH v14 7/8] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2021-10-17 17:27 ` Alexey Baturo [this message]
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