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[81.36.146.213]) by smtp.gmail.com with ESMTPSA id k22sm10947852wrd.59.2021.10.17.15.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Oct 2021 15:52:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 00/17] MIPS patches for 2021-10-18 Date: Mon, 18 Oct 2021 00:52:28 +0200 Message-Id: <20211017225245.2618892-1-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit c148a0572130ff485cd2249fbdd1a3260d5e10a4= :=0D =0D Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into st= aging (2021-10-16 11:16:28 -0700)=0D =0D are available in the Git repository at:=0D =0D https://github.com/philmd/qemu.git tags/mips-20211018=0D =0D for you to fetch changes up to 2792cf20ca7eed0e354a0ed731422411faca4908:=0D =0D via-ide: Avoid using isa_get_irq() (2021-10-18 00:41:36 +0200)=0D =0D ----------------------------------------------------------------=0D MIPS patches queue=0D =0D Hardware emulation:=0D - Generate FDT blob for Boston machine (Jiaxun)=0D - VIA chipset cleanups (Zoltan)=0D =0D TCG:=0D - Use tcg_constant() in Compact branch and MSA opcodes=0D - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6=0D - Fix DEXTRV_S.H DSP opcode=0D - Remove unused TCG temporary for some DSP opcodes=0D =0D ----------------------------------------------------------------=0D =0D BALATON Zoltan (4):=0D via-ide: Set user_creatable to false=0D vt82c686: Move common code to via_isa_realize=0D vt82c686: Add a method to VIA_ISA to raise ISA interrupts=0D via-ide: Avoid using isa_get_irq()=0D =0D Jiaxun Yang (3):=0D hw/mips/boston: Massage memory map information=0D hw/mips/boston: Allow loading elf kernel and dtb=0D hw/mips/boston: Add FDT generator=0D =0D Philippe Mathieu-Daud=C3=A9 (10):=0D target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6=0D target/mips: Remove unused register from MSA 2R/2RF instruction format=0D target/mips: Use tcg_constant_i32() in gen_msa_elm_df()=0D target/mips: Use tcg_constant_i32() in gen_msa_2rf()=0D target/mips: Use tcg_constant_i32() in gen_msa_2r()=0D target/mips: Use tcg_constant_i32() in gen_msa_3rf()=0D target/mips: Use explicit extract32() calls in gen_msa_i5()=0D target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()=0D target/mips: Fix DEXTRV_S.H DSP opcode=0D target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()=0D =0D include/hw/isa/vt82c686.h | 4 +=0D hw/ide/via.c | 7 +-=0D hw/isa/vt82c686.c | 75 +++--=0D hw/mips/boston.c | 371 +++++++++++++++++++++--=0D target/mips/tcg/msa_translate.c | 51 ++--=0D target/mips/tcg/translate.c | 11 +-=0D target/mips/tcg/nanomips_translate.c.inc | 6 +=0D 7 files changed, 415 insertions(+), 110 deletions(-)=0D =0D -- =0D 2.31.1=0D =0D