From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Huacai Chen" <chenhuacai@kernel.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paul Burton" <paulburton@kernel.org>
Subject: [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts
Date: Mon, 18 Oct 2021 00:52:44 +0200 [thread overview]
Message-ID: <20211017225245.2618892-17-f4bug@amsat.org> (raw)
In-Reply-To: <20211017225245.2618892-1-f4bug@amsat.org>
From: BALATON Zoltan <balaton@eik.bme.hu>
Other functions in the VT82xx chips need to raise ISA interrupts. Keep
a reference to them in the device state and add via_isa_set_irq() to
allow setting their state.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/isa/vt82c686.h | 4 ++++
hw/isa/vt82c686.c | 10 +++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h
index 0f01aaa4710..56ac141be38 100644
--- a/include/hw/isa/vt82c686.h
+++ b/include/hw/isa/vt82c686.h
@@ -1,6 +1,8 @@
#ifndef HW_VT82C686_H
#define HW_VT82C686_H
+#include "hw/pci/pci.h"
+
#define TYPE_VT82C686B_ISA "vt82c686b-isa"
#define TYPE_VT82C686B_PM "vt82c686b-pm"
#define TYPE_VT8231_ISA "vt8231-isa"
@@ -8,4 +10,6 @@
#define TYPE_VIA_AC97 "via-ac97"
#define TYPE_VIA_MC97 "via-mc97"
+void via_isa_set_irq(PCIDevice *d, int n, int level);
+
#endif
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 5b41539f2cd..8f656251b8d 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -542,6 +542,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA)
struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
+ qemu_irq *isa_irqs;
ISABus *isa_bus;
ViaSuperIOState *via_sio;
};
@@ -567,6 +568,12 @@ static const TypeInfo via_isa_info = {
},
};
+void via_isa_set_irq(PCIDevice *d, int n, int level)
+{
+ ViaISAState *s = VIA_ISA(d);
+ qemu_set_irq(s->isa_irqs[n], level);
+}
+
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
@@ -584,7 +591,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d),
&error_fatal);
- isa_bus_irqs(s->isa_bus, i8259_init(s->isa_bus, *isa_irq));
+ s->isa_irqs = i8259_init(s->isa_bus, *isa_irq);
+ isa_bus_irqs(s->isa_bus, s->isa_irqs);
i8254_pit_init(s->isa_bus, 0x40, 0, NULL);
i8257_dma_init(s->isa_bus, 0);
mc146818_rtc_init(s->isa_bus, 2000, NULL);
--
2.31.1
next prev parent reply other threads:[~2021-10-17 23:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-17 22:52 [PULL 00/17] MIPS patches for 2021-10-18 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 02/17] hw/mips/boston: Massage memory map information Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 04/17] hw/mips/boston: Add FDT generator Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 14/17] via-ide: Set user_creatable to false Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 15/17] vt82c686: Move common code to via_isa_realize Philippe Mathieu-Daudé
2021-10-17 22:52 ` Philippe Mathieu-Daudé [this message]
2021-10-17 22:52 ` [PULL 17/17] via-ide: Avoid using isa_get_irq() Philippe Mathieu-Daudé
2021-10-18 18:41 ` [PULL 00/17] MIPS patches for 2021-10-18 Richard Henderson
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