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[81.36.146.213]) by smtp.gmail.com with ESMTPSA id p8sm10491575wmg.15.2021.10.17.15.54.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Oct 2021 15:54:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts Date: Mon, 18 Oct 2021 00:52:44 +0200 Message-Id: <20211017225245.2618892-17-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211017225245.2618892-1-f4bug@amsat.org> References: <20211017225245.2618892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: BALATON Zoltan Other functions in the VT82xx chips need to raise ISA interrupts. Keep a reference to them in the device state and add via_isa_set_irq() to allow setting their state. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/isa/vt82c686.h | 4 ++++ hw/isa/vt82c686.c | 10 +++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index 0f01aaa4710..56ac141be38 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -1,6 +1,8 @@ #ifndef HW_VT82C686_H #define HW_VT82C686_H +#include "hw/pci/pci.h" + #define TYPE_VT82C686B_ISA "vt82c686b-isa" #define TYPE_VT82C686B_PM "vt82c686b-pm" #define TYPE_VT8231_ISA "vt8231-isa" @@ -8,4 +10,6 @@ #define TYPE_VIA_AC97 "via-ac97" #define TYPE_VIA_MC97 "via-mc97" +void via_isa_set_irq(PCIDevice *d, int n, int level); + #endif diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 5b41539f2cd..8f656251b8d 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -542,6 +542,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) struct ViaISAState { PCIDevice dev; qemu_irq cpu_intr; + qemu_irq *isa_irqs; ISABus *isa_bus; ViaSuperIOState *via_sio; }; @@ -567,6 +568,12 @@ static const TypeInfo via_isa_info = { }, }; +void via_isa_set_irq(PCIDevice *d, int n, int level) +{ + ViaISAState *s = VIA_ISA(d); + qemu_set_irq(s->isa_irqs[n], level); +} + static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { ViaISAState *s = opaque; @@ -584,7 +591,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp) isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), &error_fatal); - isa_bus_irqs(s->isa_bus, i8259_init(s->isa_bus, *isa_irq)); + s->isa_irqs = i8259_init(s->isa_bus, *isa_irq); + isa_bus_irqs(s->isa_bus, s->isa_irqs); i8254_pit_init(s->isa_bus, 0x40, 0, NULL); i8257_dma_init(s->isa_bus, 0); mc146818_rtc_init(s->isa_bus, 2000, NULL); -- 2.31.1