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[81.36.146.213]) by smtp.gmail.com with ESMTPSA id z6sm11193001wro.25.2021.10.17.15.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Oct 2021 15:53:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format Date: Mon, 18 Oct 2021 00:52:33 +0200 Message-Id: <20211017225245.2618892-6-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211017225245.2618892-1-f4bug@amsat.org> References: <20211017225245.2618892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions") and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added the MSA 2R/2RF instructions. However these instructions don't use any target vector register, so remove the unused TCG temporaries. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211003175743.3738710-2-f4bug@amsat.org> --- target/mips/tcg/msa_translate.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 8170a8df26b..ee6424126f7 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -1942,13 +1942,11 @@ static void gen_msa_2r(DisasContext *ctx) { #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0x7 << 18))) - uint8_t wt = (ctx->opcode >> 16) & 0x1f; uint8_t ws = (ctx->opcode >> 11) & 0x1f; uint8_t wd = (ctx->opcode >> 6) & 0x1f; uint8_t df = (ctx->opcode >> 16) & 0x3; TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); TCGv_i32 tdf = tcg_const_i32(df); switch (MASK_MSA_2R(ctx->opcode)) { @@ -2018,7 +2016,6 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); tcg_temp_free_i32(tdf); } @@ -2026,13 +2023,11 @@ static void gen_msa_2rf(DisasContext *ctx) { #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0xf << 17))) - uint8_t wt = (ctx->opcode >> 16) & 0x1f; uint8_t ws = (ctx->opcode >> 11) & 0x1f; uint8_t wd = (ctx->opcode >> 6) & 0x1f; uint8_t df = (ctx->opcode >> 16) & 0x1; TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); /* adjust df value for floating-point instruction */ TCGv_i32 tdf = tcg_const_i32(df + 2); @@ -2089,7 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx) tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); tcg_temp_free_i32(tdf); } -- 2.31.1