From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Huacai Chen" <chenhuacai@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Paul Burton" <paulburton@kernel.org>
Subject: [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf()
Date: Mon, 18 Oct 2021 00:52:35 +0200 [thread overview]
Message-ID: <20211017225245.2618892-8-f4bug@amsat.org> (raw)
In-Reply-To: <20211017225245.2618892-1-f4bug@amsat.org>
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-4-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 20036ae4968..5e8f80f2f23 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -2028,7 +2028,7 @@ static void gen_msa_2rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
/* adjust df value for floating-point instruction */
- TCGv_i32 tdf = tcg_const_i32(df + 2);
+ TCGv_i32 tdf = tcg_constant_i32(df + 2);
switch (MASK_MSA_2RF(ctx->opcode)) {
case OPC_FCLASS_df:
@@ -2083,7 +2083,6 @@ static void gen_msa_2rf(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(tdf);
}
static void gen_msa_vec_v(DisasContext *ctx)
--
2.31.1
next prev parent reply other threads:[~2021-10-17 23:02 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-17 22:52 [PULL 00/17] MIPS patches for 2021-10-18 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 02/17] hw/mips/boston: Massage memory map information Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 04/17] hw/mips/boston: Add FDT generator Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() Philippe Mathieu-Daudé
2021-10-17 22:52 ` Philippe Mathieu-Daudé [this message]
2021-10-17 22:52 ` [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 14/17] via-ide: Set user_creatable to false Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 15/17] vt82c686: Move common code to via_isa_realize Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 17/17] via-ide: Avoid using isa_get_irq() Philippe Mathieu-Daudé
2021-10-18 18:41 ` [PULL 00/17] MIPS patches for 2021-10-18 Richard Henderson
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