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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
	Igor Mammedov <imammedo@redhat.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
Date: Mon, 18 Oct 2021 23:38:24 +0800	[thread overview]
Message-ID: <20211018153829.24382-1-bmeng.cn@gmail.com> (raw)

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/microchip_pfsoc.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e475b6d511..f10f55b488 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -459,7 +459,6 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     const MemMapEntry *memmap = microchip_pfsoc_memmap;
     MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *mem_low = g_new(MemoryRegion, 1);
     MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
@@ -486,16 +485,13 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* Register RAM */
-    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
-                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-                           &error_fatal);
     memory_region_init_alias(mem_low_alias, NULL,
                              "microchip.icicle.kit.ram_low.alias",
-                             mem_low, 0,
+                             machine->ram, 0,
                              memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-                                mem_low);
+                                machine->ram);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
                                 mem_low_alias);
@@ -606,6 +602,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                    MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
     mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpus = mc->min_cpus;
+    mc->default_ram_id = "microchip.icicle.kit.ram_low";
 
     /*
      * Map 513 MiB high memory, the mimimum required high memory size, because
-- 
2.25.1



             reply	other threads:[~2021-10-18 15:42 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-18 15:38 Bin Meng [this message]
2021-10-18 15:38 ` [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-19  7:11   ` Igor Mammedov
2021-10-19 12:57     ` Bin Meng
2021-10-18 15:38 ` [PATCH 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-19  7:12   ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-19  7:15   ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-19  7:16   ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 6/6] hw/riscv: spike: " Bin Meng
2021-10-19  7:17   ` Igor Mammedov
2021-10-18 15:51 ` [PATCH 1/6] hw/riscv: microchip_pfsoc: " Philippe Mathieu-Daudé
2021-10-18 16:00   ` Bin Meng
2021-10-19  7:39 ` Igor Mammedov
2021-10-20  1:55   ` Bin Meng
2021-10-20  8:32     ` Igor Mammedov

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