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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>,
	Igor Mammedov <imammedo@redhat.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Date: Mon, 18 Oct 2021 23:38:29 +0800	[thread overview]
Message-ID: <20211018153829.24382-6-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20211018153829.24382-1-bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/spike.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 79ae355ae2..288d69cd9f 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -180,7 +180,6 @@ static void spike_board_init(MachineState *machine)
     const MemMapEntry *memmap = spike_memmap;
     SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     target_ulong firmware_end_addr, kernel_start_addr;
     uint32_t fdt_load_addr;
@@ -239,10 +238,8 @@ static void spike_board_init(MachineState *machine)
     }
 
     /* register system main memory (actual RAM) */
-    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
-        main_mem);
+        machine->ram);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -326,6 +323,7 @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->default_ram_id = "riscv.spike.ram";
 }
 
 static const TypeInfo spike_machine_typeinfo = {
-- 
2.25.1



  parent reply	other threads:[~2021-10-18 15:51 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-18 15:38 [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id Bin Meng
2021-10-18 15:38 ` [PATCH 2/6] hw/riscv: opentitan: " Bin Meng
2021-10-19  7:11   ` Igor Mammedov
2021-10-19 12:57     ` Bin Meng
2021-10-18 15:38 ` [PATCH 3/6] hw/riscv: shakti_c: " Bin Meng
2021-10-19  7:12   ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 4/6] hw/riscv: sifive_e: " Bin Meng
2021-10-19  7:15   ` Igor Mammedov
2021-10-18 15:38 ` [PATCH 5/6] hw/riscv: sifive_u: " Bin Meng
2021-10-19  7:16   ` Igor Mammedov
2021-10-18 15:38 ` Bin Meng [this message]
2021-10-19  7:17   ` [PATCH 6/6] hw/riscv: spike: " Igor Mammedov
2021-10-18 15:51 ` [PATCH 1/6] hw/riscv: microchip_pfsoc: " Philippe Mathieu-Daudé
2021-10-18 16:00   ` Bin Meng
2021-10-19  7:39 ` Igor Mammedov
2021-10-20  1:55   ` Bin Meng
2021-10-20  8:32     ` Igor Mammedov

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