From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump
Date: Mon, 18 Oct 2021 17:01:07 -0700 [thread overview]
Message-ID: <20211019000108.3678724-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org>
Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 99 +++++++++++++++++++++++++---------------------
1 file changed, 55 insertions(+), 44 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f352c2b74c..b81b880900 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -241,52 +241,63 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
#endif
qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc);
+
#ifndef CONFIG_USER_ONLY
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
- (target_ulong)(env->mstatus >> 32));
+ {
+ static const struct {
+ const char *name;
+ int csrno;
+ int misa;
+ bool rv32;
+ } dump_csrs[] = {
+ { "mhartid", CSR_MHARTID },
+ { "mstatus", CSR_MSTATUS },
+ { "mstatush", CSR_MSTATUSH, 0, true },
+ { "hstatus", CSR_HSTATUS, RVH },
+ { "vsstatus", CSR_VSSTATUS, RVH },
+ { "mip", CSR_MIP },
+ { "mie", CSR_MIE },
+ { "mideleg", CSR_MIDELEG },
+ { "hideleg", CSR_HIDELEG, RVH },
+ { "medeleg", CSR_MEDELEG },
+ { "hedeleg", CSR_HEDELEG, RVH },
+ { "mtvec", CSR_MTVEC },
+ { "stvec", CSR_STVEC },
+ { "vstvec", CSR_VSTVEC, RVH },
+ { "mepc", CSR_MEPC },
+ { "sepc", CSR_SEPC },
+ { "vsepc", CSR_VSEPC, RVH },
+ { "mcause", CSR_MCAUSE },
+ { "scause", CSR_SCAUSE },
+ { "vscause", CSR_VSCAUSE, RVH },
+ { "mtval", CSR_MTVAL },
+ { "stval", CSR_STVAL },
+ { "htval", CSR_HTVAL, RVH },
+ { "mtval2", CSR_MTVAL2, RVH },
+ { "mscratch", CSR_MSCRATCH },
+ { "sscratch", CSR_SSCRATCH },
+ { "satp", CSR_SATP},
+ };
+
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
+
+ for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
+ target_ulong val = 0;
+ RISCVException result;
+
+ if (dump_csrs[i].misa && !riscv_has_ext(env, dump_csrs[i].misa)) {
+ continue;
+ }
+ if (dump_csrs[i].rv32 && !rv32) {
+ continue;
+ }
+
+ result = riscv_csrrw_debug(env, dump_csrs[i].csrno, &val, 0, 0);
+ assert(result == RISCV_EXCP_NONE);
+ qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+ dump_csrs[i].name, val);
+ }
}
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
- (target_ulong)env->vsstatus);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval);
- if (riscv_has_ext(env, RVH)) {
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
- }
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
- qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
#endif
for (i = 0; i < 32; i++) {
--
2.25.1
next prev parent reply other threads:[~2021-10-19 0:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 0:00 [PATCH v4 00/16] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-19 0:00 ` [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-19 0:00 ` [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-19 0:00 ` [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-19 0:00 ` [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-19 0:00 ` [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-19 0:00 ` [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-19 0:00 ` [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-19 0:01 ` [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-19 0:01 ` [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-19 2:24 ` LIU Zhiwei
2021-10-19 2:30 ` Richard Henderson
2021-10-19 0:01 ` [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-19 0:01 ` [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-19 0:01 ` [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-19 0:01 ` [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-19 0:01 ` [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump Richard Henderson
2021-10-19 2:42 ` LIU Zhiwei
2021-10-19 0:01 ` Richard Henderson [this message]
2021-10-19 2:55 ` [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-19 0:01 ` [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand Richard Henderson
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