From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64
Date: Mon, 18 Oct 2021 17:00:58 -0700 [thread overview]
Message-ID: <20211019000108.3678724-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211019000108.3678724-1-richard.henderson@linaro.org>
Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 081a5ca34d..d60279b295 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -743,7 +743,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
static bool amo_check64(DisasContext *s, arg_rwdvm* a)
{
- return !is_32bit(s) && amo_check(s, a);
+ REQUIRE_64BIT(s);
+ return amo_check(s, a);
}
GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
--
2.25.1
next prev parent reply other threads:[~2021-10-19 0:09 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 0:00 [PATCH v4 00/16] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-19 0:00 ` [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-19 0:00 ` [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-19 0:00 ` [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-19 0:00 ` [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-19 0:00 ` [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-19 0:00 ` Richard Henderson [this message]
2021-10-19 0:00 ` [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-19 0:01 ` [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-19 0:01 ` [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-19 2:24 ` LIU Zhiwei
2021-10-19 2:30 ` Richard Henderson
2021-10-19 0:01 ` [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-19 0:01 ` [PATCH v4 11/16] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-19 0:01 ` [PATCH v4 12/16] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-19 0:01 ` [PATCH v4 13/16] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-19 0:01 ` [PATCH v4 14/16] target/riscv: Align gprs and fprs in cpu_dump Richard Henderson
2021-10-19 2:42 ` LIU Zhiwei
2021-10-19 0:01 ` [PATCH v4 15/16] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-19 2:55 ` Richard Henderson
2021-10-19 0:01 ` [PATCH v4 16/16] target/riscv: Compute mstatus.sd on demand Richard Henderson
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